D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
Read-Only, Pin Configured 24-Bit - ADC
with Excitation Current Sources
AD7783
FEATURES
Single-Channel, 24-Bit - ADC
Pin Configurable (No Programmable Registers)
ISOURCE Select™
Pin Programmable Input Ranges (±2.56 V or
±160
mV)
Fixed 19.79 Hz Update Rate
Simultaneous 50 Hz and 60 Hz Rejection
24-Bit No Missing Codes
18.5-Bit p-p Resolution (±2.56 V Range)
16.5-Bit p-p Resolution (±160 mV Range)
INTERFACE
Master or Slave Mode of Operation
Slave Mode
3-Wire Serial
SPI
®
, QSPI™, MICROWIRE™, and DSP-Compatible
Schmitt Trigger on SCLK
POWER
Specified for Single 3 V and 5 V Operation
Normal: 1.3 mA @ 3 V
Power-Down: 9 A
ON-CHIP FUNCTIONS
Rail-to-Rail Input Buffer and PGA
APPLICATIONS
Sensor Measurement
Industrial Process Control
Temperature Measurement
Pressure Measurement
Weigh Scales
Portable Instrumentation
ANALOG
INPUT
CURRENT
SOURCES
REFERENCE
INPUT
AIN(+)
AIN(–)
IOUT1
IOUT2
REFIN(+)
REFIN(–)
GND
FUNCTIONAL BLOCK DIAGRAM
V
DD
IEXC1
200 A
GND
V
DD
REFIN(+)
REFIN(–)
XTAL1
XTAL2
IEXC2
200 A
IOUT1
IOUT2
IPIN
OSCILLATOR
AND
PLL
AIN(+)
AIN(–)
MUX
BUF
PGA
24-BIT -
ADC
SERIAL
INTERFACE
AND
CONTROL
LOGIC
DOUT/RDY
SCLK
MODE
AD7783
RANGE
CS
BASIC CONNECTION DIAGRAM
POWER SUPPLY
V
DD
AD7783
CS
DOUT/RDY
SCLK
XTAL1
XTAL2
32.768kHz
CRYSTAL
DIGITAL
INTERFACE
GENERAL DESCRIPTION
The AD7783 is a complete analog front end for low frequency
measurement applications. The 24-bit sigma-delta ADC con-
tains one fully differential input channel that can be configured
with a gain of 1 or 16 allowing full-scale input signal ranges of
±
2.56 V or
±
160 mV from a +2.5 V differential reference input.
It also contains two 200
mA
integrated current sources.
The AD7783 has an extremely simple, read-only digital inter-
face that can be operated in master mode or slave mode.
There are no on-chip registers to be programmed. The input
signal range and current source selection are configured using
two external pins.
The device operates from a 32.768 kHz crystal with an on-chip
PLL generating the required internal operating frequency. The
output data rate from the part is fixed via the master clock at
19.79 Hz and provides simultaneous 50 Hz and 60 Hz rejection
at this update rate. At this update rate, 18-bit p-p resolution can
be obtained.
The part operates from a single 3 V or 5 V supply. When oper-
ating from 3 V supplies, the power dissipation for the part is
3.9 mW. The AD7783 is available in a 16-lead TSSOP.
Another part in the AD778x family is the AD7782. It is similar
to the AD7783 except it has no integrated current sources and
two differential input channels.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2004 Analog Devices, Inc. All rights reserved.
AD7783–SPECIFICATIONS
1
(V =T 2.7toVTto 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V; REFIN(–) = GND;
GND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal; all specifications
, unless otherwise noted.)
DD
MIN
MAX
Parameter
ADC CHANNEL SPECIFICATION
Output Update Rate
ADC CHANNEL
No Missing Codes
2
Resolution
Output Noise
Integral Nonlinearity
Offset Error
Offset Error Drift versus Temperature
Full-Scale Error
Gain Drift versus Temperature
Power Supply Rejection (PSR)
ANALOG INPUTS
Differential Input Voltage Ranges
ADC Range Matching
Absolute AIN Voltage Limits
Analog Input Current
2
DC Input Current
DC Input Current Drift
Normal-Mode Rejection
2, 3
@ 50 Hz
@ 60 Hz
Common-Mode Rejection
@ DC
@ 50 Hz
2
@ 60 Hz
2
REFERENCE INPUT
REFIN Voltage
REFIN Voltage Range
2
Absolute REFIN Voltage Limits
2
Average Reference Input Current
Average Reference Input Current Drift
Normal-Mode Rejection
2, 3
@ 50 Hz
@ 60 Hz
Common-Mode Rejection
@ DC
@ 50 Hz
@ 60 Hz
EXCITATION CURRENT SOURCES
(IEXC1, IEXC2)
Output Current
Initial Tolerance at 25∞C
Drift
Initial Current Matching at 25∞C
Drift Matching
Line Regulation
Load Regulation
Output Compliance
AD7783B
19.79
24
16
18
See Table I
±
10
±
3
±
10
±
10
±
0.5
100
85
±
160
±
2.56
±
2
GND + 100 mV
V
DD
– 100 mV
±
1
±
5
60
94
105
100
100
2.5
1
V
DD
GND – 30 mV
V
DD
+ 30 mV
0.5
±
0.01
60
94
100
110
110
Unit
Hz nom
Bits min
Bits p-p
Bits p-p
ppm of FSR max
mV
typ
nV/∞C typ
mV
typ
ppm/∞C typ
dB typ
dB typ
mV nom
V nom
mV
typ
V min
V max
nA max
pA/∞C typ
dB min
dB min
dB min
dB min
dB min
V nom
V min
V max
V min
V max
mA/V
typ
nA/V/∞C typ
dB min
dB min
dB typ
dB typ
dB typ
Test Conditions
±
160 mV Range, RANGE = 0
±
2.56 V Range, RANGE = 1
Typically 2 ppm,
FSR
=
AIN(+) = AIN(–) = 2.5 V
V
DD
= 3 V
Input Range =
±
160 mV, V
IN
= 1/16 V
Input Range =
±
2.56 V, V
IN
= 1 V
Range = 0
Range = 1
Input Voltage = 159 mV on Both Ranges
2
¥
1.024
REFIN
Gain
50 Hz
±
1 Hz
60 Hz
±
1 Hz
Input Range =
±
160 mV, V
IN
= 1/16 V
125 dB typ,
110 dB typ when Input Range =
±
2.56 V
50 Hz
±
1 Hz
60 Hz
±
1 Hz
REFIN = REFIN(+) – REFIN(–)
50 Hz
±
1 Hz
60 Hz
±
1 Hz
Input Range =
±
160 mV, V
IN
= 1/16 V
50 Hz
±
1 Hz
60 Hz
±
1 Hz
200
±
10
200
±
2.5
20
2.5
300
V
DD
– 0.6
GND – 30 mV
mA
% typ
ppm/∞C typ
% max
ppm/∞C typ
mA/V
max
nA/V typ
V max
V min
–2–
No Load
V
DD
= 5 V
±
5%. Typically 1.25
mA/V.
REV. B
AD7783
Parameter
LOGIC INPUTS
All Inputs Except SCLK and XTAL1
2
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
SCLK Only (Schmitt-Triggered Input)
2
V
T(+)
V
T(–)
V
T(+)
– V
T(–)
V
T(+)
V
T(–)
V
T(+)
– V
T(–)
XTAL1 Only
2
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
Input Currents
AD7783B
Unit
Test Conditions
0.8
0.4
2.0
1.4/2
0.8/1.4
0.3/0.85
0.95/2
0.4/1.1
0.3/0.85
0.8
3.5
0.4
2.5
±
1
–70
10
V
DD
– 0.6
0.4
4
0.4
±
10
±
10
Offset Binary
300
V max
V max
V min
V min/V max
V min/V max
V min/V max
V min/V max
V min/V max
V min/V max
V max
V min
V max
V min
mA
max
mA
max
pF typ
V min
V max
V min
V max
mA
max
pF typ
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 3 V or 5 V
V
DD
= 5 V
V
DD
= 5 V
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 3 V
V
DD
= 3 V
V
DD
= 5 V
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 3 V
V
IN
= V
DD
V
IN
= GND, Typically –40
mA
at 5 V and
–20
mA
at 3 V
All Digital Inputs
V
DD
= 3 V, I
SOURCE
= 100
mA
V
DD
= 3 V, I
SINK
= 100
mA
V
DD
= 5 V, I
SOURCE
= 200
mA
V
DD
= 5 V, I
SINK
= 1.6 mA
Input Capacitance
LOGIC OUTPUTS (Excluding XTAL2)
V
OH
, Output High Voltage
2
V
OL
, Output Low Voltage
2
V
OH
, Output High Voltage
2
V
OL
, Output Low Voltage
2
Floating-State Leakage Current
Floating-State Output Capacitance
Data Output Coding
START-UP TIME
From Power-On
POWER REQUIREMENTS
Power Supply Voltage
V
DD
– GND
Power Supply Currents
I
DD
Current (Normal Mode)
4
I
DD
(Power-Down Mode,
CS
= 1)
ms typ
2.7/3.6
4.75/5.25
1.5
1.7
9
24
V min/V max
V min/V max
mA max
mA max
mA
max
mA
max
V
DD
= 3 V nom
V
DD
= 5 V nom
V
DD
= 3 V, 1.3 mA typ
V
DD
= 5 V, 1.5 mA typ
V
DD
= 3 V, 6
mA
typ
V
DD
= 5 V, 20
mA
typ
NOTES
1
Temperature range –40∞C to +85∞C.
2
Guaranteed by design and/or characterization data on production release.
3
When a 28.8 kHz crystal is used, normal-mode rejection is improved so that the rejection equals 75 dB at 50 Hz
±
1 Hz and equals 66 dB at 60 Hz
±
1 Hz.
4
Normal mode refers to the case where the ADC is running.
Specifications subject to change without notice.
REV. B
–3–
AD7783
(V
DD
= 2.7 V to 3.6 V or V
DD
= 4.75 V to 5.25 V; GND = 0 V; XTAL = 32.768 kHz;
Input Logic 0 = 0 V, Logic 1 = V
DD
, unless otherwise noted.)
Parameter
t
1
t
ADC
t
2
t
3
t
4 3
t
7 5
t
8
t
9
Slave Mode Timing
t
5
t
6
Master Mode Timing
t
5
t
6
t
10
Limit at T
MIN
, T
MAX
(B Version)
30.5176
50.54
0
60
80
2
¥
t
ADC
0
60
80
10
80
0
10
80
100
100
t
1
/2
t
1
/2
t
1
/2
3t
1
/2
Unit
ms
typ
ms typ
ns min
ns max
ns max
ns typ
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns max
ns min
ns min
ms
typ
ms
typ
ms
min
ms
max
Conditions/Comments
Crystal Oscillator Period
19.79 Hz Update Rate
CS
Falling Edge to DOUT Active
V
DD
= 4.75 V to 5.25 V
V
DD
= 2.7 V to 3.6 V
Channel Settling Time
SCLK Active Edge to Data Valid Delay
4
V
DD
= 4.75 V to 5.25 V
V
DD
= 2.7 V to 3.6 V
Bus Relinquish Time after
CS
Inactive Edge
CS
Rising Edge to SCLK Inactive Edge Hold Time
SCLK Inactive to DOUT High
TIMING CHARACTERISTICS
1, 2
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK High Pulse Width
SCLK Low Pulse Width
DOUT Low to First SCLK Active Edge
4
NOTES
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
See Figure 2.
3
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
4
SCLK active edge is falling edge of SCLK.
5
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means the times quoted in the timing characteristics are the true bus relin-
quish times of the part and as such are independent of external bus loading capacitances.
I
SINK
(1.6mA WITH V
DD
= 5V
100 A WITH V
DD
= 3V)
TO OUTPUT
PIN
1.6V
50pF
I
SOURCE
( 200 A WITH V
DD
= 5V
100 A WITH V
DD
= 3V)
Figure 1. Load Circuit for Timing Characterization
–4–
REV. B
