Changes to Ordering Guide .......................................................... 27
2/01—Rev. A to Rev. B
Rev. C | Page 2 of 28
AD7890
SPECIFICATIONS
V
DD
= 5 V, AGND = DGND = 0 V, REF IN = 2.5 V, f
CLK IN
= 2.5 MHz external, MUX OUT connect to SHA IN. All specifications T
MIN
to
T
MAX
, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal to (Noise + Distortion) Ratio
2
Total Harmonic Distortion (THD)
2
Peak Harmonic or Spurious Noise
2
Intermodulation Distortion
2nd Order Terms
3rd Order Terms
Channel-to-Channel Isolation
2
DC ACCURACY
Resolution
Min. Resolution for Which
No
A Versions
1
70
−77
−78
−80
−80
−80
12
12
±1
±1
±2.5
2
±2
2
±2
±5
2
B Versions
70
−77
−78
−80
−80
−80
12
12
±0.5
±1
±2.5
2
±2
2
±2
±5
2
S Version
70
−77
−78
−80
−80
−80
12
12
±1
±1
±2.5
2
±2
2
±2
±5
2
Unit
dB min
dB max
dB max
dB typ
dB typ
dB max
Bits
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Test Conditions/Comments
Using external CONVST, any channel
f
IN
= 10 kHz sine wave, f
SAMPLE
= 100 kHz
3
f
IN
= 10 kHz sine wave, f
SAMPLE
= 100 kHz
3
f
IN
= 10 kHz sine wave, f
SAMPLE
= 100 kHz
3
fa = 9 kHz, fb = 9.5 kHz, f
SAMPLE
= 100 kHz
3
f
IN
= 1 kHz sine wave
Missing Codes Are Guaranteed
Relative Accuracy
2
Differential Nonlinearity
2
Positive Full-Scale Error
2
Full-Scale Error Match
4
AD7890-2, AD7890-4
Unipolar Offset Error
2
Unipolar Offset Error Match
AD7890-10 Only
Negative Full-Scale Error
2
Bipolar Zero Error
2
Bipolar Zero Error Match
ANALOG INPUTS
AD7890-10
Input Voltage Range
Input Resistance
AD7890-4
Input Voltage Range
Input Resistance
AD7890-2
Input Voltage Range
Input Current
MUX OUT OUTPUT
Output Voltage Range
Output Resistance
AD7890-10, AD7890-4
AD7890-2
SHA IN INPUT
Input Voltage Range
Input Current
REFERENCE OUTPUT/INPUT
REF IN Input Voltage Range
Input Impedance
Input Capacitance
5
REF OUT Output Voltage
REF OUT Error @ 25°C
T
MIN
to T
MAX
REF OUT Temperature Coefficient
REF OUT Output Impedance
±10
20
0 to 4.096
11
0 to 2.5
50
0 to 2.5
3/5
2
0 to 2.5
±50
2.375/2.625
1.6
10
2.5
±10
±20
25
2
±10
20
0 to 4.096
11
0 to 2.5
50
0 to 2.5
3/5
2
0 to 2.5
±50
2.375/2.625
1.6
10
2.5
±10
±20
25
2
±10
20
0 to 4.096
11
0 to 2.5
200
0 to 2.5
3/5
2
0 to 2.5
±50
2.375/2.625
1.6
10
2.5
±10
±25
25
2
Volts
kΩ min
Volts
kΩ min
Volts
nA max
Volts
kΩ min/kΩ max
kΩ max
Volts
nA max
V min/V max
kΩ min
pF max
V nom
mV max
mV max
ppm/°C typ
kΩ nom
2.5 V ± 5%
Resistor connected to internal reference node
Assuming V
IN
is driven from low impedance
Rev. C | Page 3 of 28
AD7890
Parameter
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN
5
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Serial Data Output Coding
AD7890-10
AD7890-4
AD7890-2
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
2
,
5
POWER REQUIREMENTS
V
DD
I
DD
(Normal Mode)
I
DD
(Standby Mode)
6
@ 25°C
Power Dissipation
Normal Mode
Standby Mode @ 25°C
1
2
A Versions
1
2.4
0.8
±10
10
4.0
0.4
B Versions
2.4
0.8
±10
10
4.0
0.4
S Version
2.4
0.8
±10
10
4.0
0.4
Unit
V min
V max
μA max
pF max
V min
V max
Test Conditions/Comments
V
DD
= 5 V ± 5%
V
DD
= 5 V ± 5%
V
IN
= 0 V to V
DD
I
SOURCE
= 200 μA
I
SINK
= 1.6 mA
Twos Complement
Straight (Natural) Binary
Straight (Natural) Binary
5.9
2
5
10
15
50
75
5.9
2
5
10
15
50
75
5.9
2
5
10
15
50
75
μs max
μs max
V nom
mA max
μA typ
mW max
μW typ
± 5% for specified performance
Logic inputs = 0 V or V
DD
Logic inputs = 0 V or V
DD
Typically 30 mW
f
CLK IN
= 2.5 MHz, MUX OUT, connected to
SHA IN
Temperature ranges are as follows: A, B Versions: −40°C to +85°C; S Version: −55°C to +125°C.
See the Terminology section.
3
This sample rate is only achievable when using the part in external clocking mode.
4
Full-scale error match applies to positive full scale for the AD7890-2 and AD7890-4. It applies to both positive and negative full scale for the AD7890-10.
5
Sample tested @ 25°C to ensure compliance.
6
Analog inputs on AD7890-10 must be at 0 V to achieve correct power-down current.
Rev. C | Page 4 of 28
AD7890
TIMING SPECIFICATIONS
V
DD
= 5 V ± 5%, AGND = DGND = 0 V, REF IN = 2.5 V, f
CLK IN
= 2.5 MHz external, MUX OUT connected to SHA IN.
Parameter
1 , 2
f
CLKIN 3
t
CLKIN IN LO
t
CLK IN HI
tr
4
tf
4
t
CONVERT
t
CST
Self-Clocking Mode
t
1
t
2 5
t
3
t
4
t
5
5
t
6
t
7 6
t
8
t
9
t
10
t
11
t
12
External Clocking Mode
t
13
t
14
5
t
15
t
16
t
17
5
t
18
t
19
6
t
19A
6
t
20
t
21
t
22
t
23
1
2
Limit at T
MIN
, T
MAX
(A, B, S Versions)
100
2.5
0.3 × t
CLK IN
0 3 × t
CLK IN
25
25
5.9
100
t
CLK IN HI
+ 50
25
t
CLK IN HI
t
CLK IN LO
20
40
50
0
t
CLK IN
+ 50
0
20
10
20
20
40
50
50
35
20
50
90
20
10
15
40
Unit
kHz min
MHz max
ns min
ns min
ns max
ns max
μs max
ns min
ns max
ns max
ns nom
ns nom
ns max
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
Conditions/Comments
Master Clock Frequency. For specified performance.
Master Clock Input Low Time.
Master Clock Input High Time.
Digital Output Rise Time. Typically 10 ns.
Digital Output Fall Time. Typically 10 ns.
Conversion Time.
CONVST Pulse Width.
RFS Low to SCLK Falling Edge.
RFS Low to Data Valid Delay.
SCLK High Pulse Width.
SCLK Low Pulse Width.
SCLK Rising Edge to Data Valid Delay.
SCLK Rising Edge to RFS Delay.
Bus Relinquish Time after Rising Edge of SCLK.
TFS Low to SCLK Falling Edge.
Data Valid to TFS Falling Edge Setup Time (A2 Address Bit).
Data Valid to SCLK Falling Edge Setup Time.
Data Valid to SCLK Falling Edge Hold Time.
TFS to SCLK Falling Edge Hold Time.
RFS Low to SCLK Falling Edge Setup Time.
RFS Low to Data Valid Delay.
SCLK High Pulse Width.
SCLK Low Pulse Width.
SCLK Rising Edge to Data Valid Delay.
RFS to SCLK Falling Edge Hold Time.
Bus Relinquish Time after Rising Edge of RFS.
Bus Relinquish Time after Rising Edge of SCLK.
TFS Low to SCLK Falling Edge Setup Time.
Data Valid to SCLK Falling Edge Setup Time.
Data Valid to SCLK Falling Edge Hold Time.
TFS to SCLK Falling Edge Hold Time.
Sample tested at −25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
See Figure 10 to Figure 13.
3
The AD7890 is production tested with f
CLK IN
at 2.5 MHz. It is guaranteed by characterization to operate at 100 kHz.
4
Specified using 10% and 90% points on waveform of interest.
5
These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
6
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
1.6mA
TO OUTPUT
PIN
2.1V
50pF
200µA
01357-002
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
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