a
FEATURES
Fast 14-Bit ADC with 5 s Conversion Time
8-Lead SOIC Package
Single 5 V Supply Operation
High Speed, Easy-to-Use, Serial Interface
On-Chip Track/Hold Amplifier
Selection of Input Ranges
10 V for AD7894-10
2.5 V for AD7894-3
0 V to +2.5 V for AD7894-2
High Input Impedance
Low Power: 20 mW Typ
Pin Compatible Upgrade of 12-Bit AD7895
5 V, 14-Bit Serial, 5 s
ADC in SO-8 Package
AD7894
FUNCTIONAL BLOCK DIAGRAM
REF IN
V
DD
AD7894
TRACK/
HOLD
14-BIT
ADC
V
IN
SIGNAL
SCALING*
CONVST
OUTPUT
REGISTER
GND
*AD7894-10, AD7894-3
BUSY
SCLK
SDATA
GENERAL DESCRIPTION
The AD7894 is a fast, 14-bit ADC that operates from a single
+5 V supply and is housed in a small 8-lead SOIC. The part
contains a 5
µs
successive approximation A/D converter, an on-
chip track/hold amplifier, an on-chip clock and a high speed
serial interface.
Output data from the AD7894 is provided via a high speed,
serial interface port. This two-wire serial interface has a serial
clock input and a serial data output with the external serial clock
accessing the serial data from the part.
In addition to the traditional dc accuracy specifications such as
linearity, full-scale and offset errors, the AD7894 is also speci-
fied for dynamic performance parameters including harmonic
distortion and signal-to-noise ratio.
The part accepts an analog input range of
±
10 V (AD7894-10),
±
2.5 V (AD7894-3), 0 V to +2.5 V (AD7894-2), and operates
from a single +5 V supply consuming only 20 mW typical.
The AD7894 features a high sampling rate mode and, for low
power applications, a proprietary automatic power-down mode
where the part automatically goes into power-down once conver-
sion is complete and “wakes up” before the next conversion
cycle.
The part is available in a small outline IC (SOIC).
PRODUCT HIGHLIGHTS
1. Fast, 14-Bit ADC in 8-Lead Package
The AD7894 contains a 5
µs
ADC, a track/hold amplifier,
control logic and a high speed serial interface, all in an 8-lead
package. This offers considerable space saving over alterna-
tive solutions.
2. Low Power, Single Supply Operation
The AD7894 operates from a single +5 V supply and con-
sumes only 20 mW. The automatic power-down mode,
where the part goes into power-down once conversion is
complete and “wakes up” before the next conversion cycle,
makes the AD7894 ideal for battery powered or portable
applications.
3. High Speed Serial Interface
The part provides high speed serial data and serial clock lines
allowing for an easy, two-wire serial interface arrangement.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
AD7894–SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
2
Signal to (Noise + Distortion) Ratio
3
@ +25°C
T
MIN
to T
MAX
Total Harmonic Distortion (THD)
3
Peak Harmonic or Spurious Noise
3
Intermodulation Distortion (IMD)
3
2nd Order Terms
3rd Order Terms
DC ACCURACY
Resolution
Minimum Resolution for Which
No Missing Codes Are Guaranteed
Relative Accuracy
3
Differential Nonlinearity
3
AD7894-2
Positive Gain Error
3
Unipolar Offset Error
AD7894-10, AD7894-3 Only
Positive Gain Error
3
Negative Gain Error
3
Bipolar Zero Error
ANALOG INPUT
AD7894-10
Input Voltage Range
Input Current
AD7894-3
Input Voltage Range
Input Current
AD7894-2
Input Voltage Range
Input Current
REFERENCE INPUT
REF IN Input Voltage Range
Input Current
Input Capacitance
4
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN4
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Output Coding
AD7894-10, AD7894-3
AD7894-2
CONVERSION RATE
Conversion Time
Mode 1 Operation
Mode 2 Operation
5
Track/Hold Acquisition Time
3
SAMPLE AND HOLD
–3 dB Small Signal Bandwidth
Aperture Jitter
A Versions
l
78
77
–86
–92
–92
–92
14
14
±
2
–1 to +1.5
±
12
±
8
±
8
±
8
±
10
(V
DD
= +5 V 5%, GND = 0 V, REF IN = +2.5 V. All specifications T
MIN
to T
MAX
unless
otherwise noted.)
B Versions
1
Units
Test Conditions/Comments
78
77
–86
–92
–92
–92
14
14
±
1.5
–1 to +1.5
±
10
±
6
±
6
±
6
±
8
dB min
dB min
dB max
dB typ
dB typ
dB typ
Bits
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
f
IN
= 70 kHz Sine Wave, f
SAMPLE
= 160 kHz
See Figure 14
f
IN
= 10 kHz Sine Wave, f
SAMPLE
= 160 kHz,
Typically –87 dB. See Figure 15
f
IN
= 10 kHz Sine Wave, f
SAMPLE
= 160 kHz
fa = 9 kHz, fb
=
9.5 kHz, f
SAMPLE
= 160 kHz
±
10
2
±
2.5
1.5
0 to +2.5
500
2.375/2.625
1
10
2.4
0.8
±
10
10
4.0
0.4
±
10
2
±
2.5
1.5
0 to +2.5
500
2.375/2.625
1
10
2.4
0.8
±
10
10
4.0
0.4
V
mA max
V
mA max
V
nA max
V min/V max
µA
max
pF max
V min
V max
µA
max
pF max
V min
V max
See Analog Input Section
See Analog Input Section
2.5 V
±
5%
V
DD
= 5 V
±
5%
V
DD
= 5 V
±
5%
V
IN
= 0 V to V
DD
I
SOURCE
= 400
µA
I
SINK
= 1.6 mA
Twos Complement
Straight (Natural) Binary
5
10
0.35
7.5
50
5
10
0.35
7.5
50
µs
max
µs
max
µs
max
MHz typ
ps typ
–2–
REV. 0
AD7894
Parameter
POWER REQUIREMENTS
V
DD
I
DD
Power Dissipation
Power-Down Mode
I
DD
@ T
MIN
to T
MAX
Power Dissipation T
MIN
to T
MAX
A Versions
l
+5
5.5
27.5
20
100
B Versions
1
Units
+5
5.5
27.5
20
100
V nom
mA max
mW max
µA
max
µW
max
Test Conditions/Comments
±
5% for Specified Performance
Digital Inputs @ V
DD
, V
DD
= 5 V
±
5%
Typically 20 mW
Digital Inputs @ GND, V
DD
= 5 V
±
5%
Typ 15
µW
NOTES
1
Temperature ranges are as follows: A, B Versions: –40°C to +85°C.
2
Applies to Mode 1 operation. See Operating Modes section.
3
See Terminology.
4
Sample tested @ +25°C to ensure compliance.
5
This 10
µs
includes the “wake-up” time from standby. This “wake-up” time is timed from the rising edge of
CONVST,
whereas conversion is timed from the falling
edge of
CONVST,
for narrow
CONVST
pulsewidth the conversion time is effectively the “wake-up” time plus conversion time, hence 10
µs.
This can be seen from
Figure 3. Note that if the
CONVST
pulsewidth is greater than 5
µs,
the effective conversion time will increase beyond 10
µs.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2
(V
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
A, B Versions
40
31.25
2
31.25
2
60
3
10
20
4
DD
= +5 V
5%, GND = 0 V, REF IN = +2.5 V)
Units
ns min
ns min
ns min
ns max
ns min
ns max
Test Conditions/Comments
CONVST
Pulsewidth
SCLK High Pulsewidth
SCLK Low Pulsewidth
Data Access Time after Falling Edge of SCLK
V
DD
= 5 V
±
5%
Data Hold Time after Falling Edge of SCLK
Bus Relinquish Time after Falling Edge of SCLK
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.
2
The SCLK maximum frequency is 16 MHz. Care must be taken when interfacing to account for the data access time, t
4
, and the setup time required for the user’s
processor. These two times will determine the maximum SCLK frequency with which the user’s system can operate. See Serial Interface section for more information.
3
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
6
, quoted in the timing characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to GND
AD7894-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
17 V
AD7894-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
7 V
AD7894-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +10 V
Reference Input Voltage to GND . . . . –0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to GND . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to GND . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 170°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7894 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD7894
ORDERING GUIDE
Model
AD7894AR-10
AD7894BR-10
AD7894AR-3
AD7894BR-3
AD7894AR-2
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
INL
±
2 LSB
±
1.5 LSB
±
2 LSB
±
1.5 LSB
±
2 LSB
Input Range
±
10 V
±
10 V
±
2.5 V
±
2.5 V
0 V to +2.5 V
SNR
77 dB
77 dB
77 dB
77 dB
77 dB
Package
Description
8-Lead Narrow Body SOIC
8-Lead Narrow Body SOIC
8-Lead Narrow Body SOIC
8-Lead Narrow Body SOIC
8-Lead Narrow Body SOIC
Package
Option
SO-8
SO-8
SO-8
SO-8
SO-8
PIN FUNCTION DESCRIPTIONS
Pin
No.
1
Pin
Mnemonic
REF IN
Description
Voltage Reference Input. An external reference source should be connected to this pin to provide the
reference voltage for the AD7894’s conversion process. The REF IN input is buffered on-chip. The
nominal reference voltage for correct operation of the AD7894 is +2.5 V.
Analog Input Channel. The analog input range is
±
10 V (AD7894-10),
±
2.5 V (AD7894-3) and 0 V to
+2.5 V (AD7894-2).
Analog Ground. Ground reference for track/hold, comparator, digital circuitry and DAC.
Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7894.
A new serial data bit is clocked out on the falling edge of this serial clock. Data is guaranteed valid for
10 ns after this falling edge so data can be accepted on the falling edge when a fast serial clock is used.
The serial clock input should be taken low at the end of the serial data transmission.
Serial Data Output. Serial data from the AD7894 is provided at this output. The serial data is clocked
out by the falling edge of SCLK, but the data can also be read on the falling edge of SCLK. This is pos-
sible because data bit N is valid for a specified time after the falling edge of SCLK (data hold time) (see
Figure 5). Sixteen bits of serial data are provided as two leading zeroes followed by the 14 bits of conver-
sion data. On the 16th falling edge of SCLK, the SDATA line is held for the data hold time and then
disabled (three-stated). Output data coding is twos complement for the AD7894-10 and AD7894-3, and
straight binary for the AD7894-2.
The BUSY pin is used to indicate when the part is doing a conversion. The BUSY pin will go high on
the falling edge of
CONVST
and will return low when the conversion is complete.
Conversion Start. Edge-triggered logic input. On the falling edge of this input, the track/hold goes into its
hold mode and conversion is initiated. If
CONVST
is low at the end of conversion, the part goes into
power-down mode. In this case, the rising edge of
CONVST
will cause the part to begin waking up.
Positive supply voltage, +5 V
±
5%.
2
3
4
V
IN
GND
SCLK
5
SDATA
6
7
BUSY
CONVST
8
V
DD
1.6mA
PIN CONFIGURATION
SOIC (SO-8)
+1.6V
TO
OUTPUT
PIN
50pF
REF IN
1
400 A
8
V
DD
7
CONVST
AD7894
TOP VIEW
GND
3
(Not to Scale)
6
BUSY
V
IN 2
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
SCLK
4
5
SDATA
–4–
REV. 0
AD7894
TERMINOLOGY
Signal to (Noise + Distortion) Ratio
Relative Accuracy
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f
S
/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal to
(Noise +
Distortion)
= (6.02
N
+ 1.76)
dB
Thus for a 14-bit converter, this is 86.04 dB.
Total Harmonic Distortion
Relative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Positive Gain Error (AD7894-10)
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal (4
×
VREF – 1 LSB) after the
Bipolar Zero Error has been adjusted out.
Positive Gain Error (AD7894-3)
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7894, it is defined as:
THD
(
dB
)
=
20 log
2
V
2
2
+
V
3
2
+
V
4
2
+
V
5
2
+
V
6
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal (VREF – 1 LSB) after the Bipolar
Zero Error has been adjusted out.
Positive Gain Error (AD7894-2)
V
1
where
V
1
is the rms amplitude of the fundamental and
V
2
,
V
3
,
V
4
,
V
5
and
V
6
are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
This is the deviation of the last code transition (11 . . . 110 to
11 . . . 111) from the ideal (VREF – 1 LSB) after the Unipolar
Offset Error has been adjusted out.
Bipolar Zero Error (AD7894-10, AD7894-3)
This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal 0 V (GND).
Unipolar Offset Error (AD7894-2)
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of the
fundamental. The value of this specification is normally deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal 1 LSB.
Negative Gain Error (AD7894-10)
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (–4
×
VREF + 1 LSB) after Bipolar
Zero Error has been adjusted out.
Negative Gain Error (AD7894-3)
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa
±
nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither
m
nor
n
is equal to zero. For example, the second order
terms include (fa + fb) and (fa – fb), while the third order terms
include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb).
The AD7894 is tested using two input frequencies. In this case,
the second and third order terms are of different significance.
The second order terms are usually distanced in frequency from
the original sine waves, while the third order terms are usually at
a frequency close to the input frequencies. As a result, the second
and third order terms are specified separately. The calculation
of the intermodulation distortion is as per the THD specification
where it is the ratio of the rms sum of the individual distortion
products to the rms amplitude of the fundamental expressed
in dBs.
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (– VREF + 1 LSB) after Bipolar
Zero Error has been adjusted out.
Track/Hold Acquisition Time
Track/Hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within
±
1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where there is a step input change on the input voltage applied
to the V
IN
input of the AD7894. This means that the user must
wait for the duration of the track/hold acquisition time after the
end of conversion or after a step input change to V
IN
before
starting another conversion, to ensure that the part operates to
specification.
REV. 0
–5–
嵌入式系统
