The AD7943, AD7945 and AD7948 are specified in the normal current mode configuration and in the biased current mode for single-supply applications.
Figures 14 and 15 are examples of normal mode operation.
2
Temperature ranges as follows: B Grades: –40°C to +85°C; T Grade: –55°C to +125°C.
3
The T Grade applies to the AD7945 only.
4
Guaranteed by design.
Specifications subject to change without notice.
–2–
REV. B
AD7943/AD7945/AD7948
SPECIFICATIONS
1
BIASED MODE
Parameter
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error @ +25°C
T
MIN
to T
MAX
Gain Temperature Coefficient
3
Output Leakage Current
I
OUT1
@ +25°C
T
MIN
to T
MAX
Input Resistance
@ I
OUT2
Pin (AD7943)
@ AGND Pin (AD7945, AD7948)
DIGITAL INPUTS
V
INH
, Input High Voltage @ V
DD
= +5 V
V
INH
, Input High Voltage @ V
DD
= +3.3 V
V
INL
, Input Low Voltage @ V
DD
= +5 V
V
INL
, Input Low Voltage @ V
DD
= +3.3 V
I
INH
, Input Current
C
IN
, Input Capacitance
3
DIGITAL OUTPUT (SRO)
Output Low Voltage (V
OL
)
Output High Voltage (V
OH
)
POWER REQUIREMENTS
V
DD
Range
Power Supply Sensitivity
3
∆Gain/∆V
DD
I
DD
(AD7943)
(AD7943: V
DD
= +3 V to +5.5 V; V
IOUT1
= V
IOUT2
= AGND = 1.23 V; V
REF
= +0 V to 2.45 V; T
A
= T
MIN
to T
MAX
, unless other-
wise noted. AD7945, AD7948: V
DD
= +3 V to +5.5 V; V
IOUT1
= AGND = 1.23 V; V
REF
= +0 V to 2.45 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
A Grades
2
Units
12
±
1
±
0.9
±
3
±
4
2
5
Bits
LSB max
LSB max
LSB max
LSB max
ppm FSR/°C typ
ppm FSR/°C max
See Terminology Section
10
100
6
6
2.4
2.1
0.8
0.6
±
1
10
0.2
V
DD
– 0.2
3.0/5.5
–75
5
nA max
nA max
kΩ min
kΩ min
V min
V min
V max
V max
µA
max
pF max
For 1 CMOS Load
V max
V min
V min/V max
dB typ
µA
max
Test Conditions/Comments
1 LSB = (V
IOUT1
– V
REF)
/2
12
= 300
µV
When
V
IOUT1
= 1.23 V and V
REF
= 0 V
All Grades Guaranteed Monotonic
over Temperature
Typically 20 nA over Temperature
This Varies with DAC Input Code
I
DD
(AD7945, AD7948)
5
µA
max
V
INH
= V
DD
– 0.1 V min, V
INL
= 0.1 V max.
SRO Open Circuit; No STB Signal; Typically
1
µA.
Typically 100
µA
with 1 MHz STB
Frequency.
V
INH
= V
DD
– 0.1 V min, V
INL
= 0.1 V max.
Typically 1
µA.
NOTES
1
These specifications apply with the devices biased up at 1.23 V for single supply applications. The model numbering reflects this by means of a “–B” suffix
(for example: AD7943AN-B). Figure 16 is an example of Biased Mode Operation.
2
Temperature ranges as follows: A Versions: –40°C to +85°C.
3
Guaranteed by design.
Specifications subject to change without notice.
REV. B
–3–
AD7943/AD7945/AD7948
NORMAL MODE
Parameter
DYNAMIC PERFORMANCE
Output Voltage Settling Time
AC PERFORMANCE CHARACTERISTICS
B Grades
600
T Grade
700
Units
ns typ
Test Conditions/Comments
To 0.01% of Full-Scale Range. V
REF
=
+10 V; DAC Latch Alternately Loaded with
All 0s and All 1s
Measured with V
REF
= 0 V. DAC Latch
Alternately Loaded with All 0s and All 1s
DAC Latch Loaded with All 0s
All 1s Loaded to DAC
All 0s Loaded to DAC
Feedthrough to the DAC Output with
LD1,
LD2
High and Alternate Loading of All 0s
and All 1s into the Input Shift Register
Feedthrough to the DAC Output with
CS
High and Alternate Loading of All 0s and
All 1s to the DAC Bus
(AD7943: V
DD
= +4.5 V to +5.5 V; V
IOUT1
= V
IOUT2
= AGND = 0 V. AD7945, AD7948: V
DD
= +4.5 V to +5.5 V; V
IOUT1
=AGND =
0 V. V
REF
= 6 V rms, 1 kHz sine wave; T
A
= T
MIN
to T
MAX
; DAC output op amp is AD843; unless otherwise noted.) These characteristics are in-
cluded for Design Guidance and are not subject to test.
Digital to Analog Glitch Impulse
Multiplying Feedthrough Error
Output Capacitance
Digital Feedthrough (AD7943)
60
–75
60
30
5
60
–75
60
30
5
nV-s typ
dB max
pF max
pF max
nV-s typ
Digital Feedthrough (AD7945, AD7948) 5
5
nV-s typ
Total Harmonic Distortion
Output Noise Spectral Density
@ 1 kHz
Specifications subject to change without notice.
–83
35
–83
35
dB typ
nV/√Hz typ All 1s Loaded to DAC. V
REF
= 0 V. Output
Op Amp Is OP07
AC PERFORMANCE CHARACTERISTICS
(AD7943: V
DD
= +3 V to +5.5 V; V
IOUT1
= V
IOUT2
= AGND = 1.23 V. AD7945, AD7948: V
DD
= +3 V to +5.5 V; V
IOUT1
= AGND =
1.23 V. V
REF
= 1 kHz, 2.45 V p-p, sine wave biased at 1.23 V; DAC output op amp is AD820; T
A
= T
MIN
to T
MAX
; unless otherwise noted.) These
characteristics are included for Design Guidance and are not subject to test.
Parameter
DYNAMIC PERFORMANCE
Output Voltage Settling Time
Digital to Analog Glitch Impulse
Multiplying Feedthrough Error
Output Capacitance
Digital Feedthrough
A Grades
5
60
–75
60
30
5
Units
µs
typ
nV-s typ
dB max
pF max
pF max
nV-s typ
Test Conditions/Comments
To 0.01% of Full-Scale Range. V
REF
= 0 V
DAC Latch Alternately Loaded with All 0s and All 1s
V
REF
= 1.23 V. DAC Register Alternately Loaded
with All 0s and All 1s
DAC Latch Loaded with All 0s
All 1s Loaded to DAC
All 0s Loaded to DAC
Feedthrough to the DAC Output with
LD1, LD2
High and Alternate Loading of All 0s and All 1s
into the Input Shift Register
Feedthrough to the DAC Output with CS High
and Alternate Loading of All 0s and All 1s to the
DAC Bus
BIASED MODE
Digital Feedthrough (AD7945, AD7948)
5
nV-s typ
Total Harmonic Distortion
Output Noise Spectral Density
@ 1 kHz
Specifications subject to change without notice.
–83
25
dB typ
nV/√Hz typ
All 1s Loaded to DAC. V
REF
= 1.23 V
–4–
REV. B
AD7943/AD7945/AD7948
AD7943 TIMING SPECIFICATIONS
1
(T
Parameter
t
STB2
t
DS
t
DH
t
SRI
t
LD
t
CLR
t
ASB
t
SV3
Limit @
V
DD
= +3 V to +3.6 V
60
15
35
55
55
55
0
60
40
10
25
35
35
35
0
35
A
= T
MIN
to T
MAX
, unless otherwise noted)
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
Description
STB Pulsewidth
Data Setup Time
Data Hold Time
SRI Data Pulsewidth
Load Pulsewidth
CLR Pulsewidth
Min Time Between Strobing Input Shift
Register and Loading DAC Register
STB Clocking Edge to SRO Data Valid Delay
Limit @
V
DD
= +4.5 V to +5.5 V
NOTES
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. tr and tf should not exceed 1
µs
on any digital input.
2
STB mark/space ratio range is 60/40 to 40/60.
3
t
SV
is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
Specifications subject to change without notice.
t
STB
STB1,
STB2,
STB4
STB3
t
DH
t
DS
t
SRI
SRI
DB11(N)
(MSB)
DB10(N)
DB0(N)
t
ASB
LD1,
LD2,
CLR
SRO
t
LD,
t
CLR
t
SV
DB10(N–1)
DB0(N–1)
Figure 1. AD7943 Timing Diagram
1.6mA
I
OL
TO OUTPUT
PIN
+2.1V
C
L
50pF
200 A
I
OH
Figure 2. Load Circuit for Digital Output Timing Specifications
