Data Sheet
FEATURES
Fully differential signal path, also used with single-sided signals
Inputs from 0.3 mV to 1 V rms, rail-to-rail outputs
Differential R
IN
= 1 kΩ; R
OUT
(each output) 75 Ω
Automatic offset compensation (optional)
Linear-in-dB and linear-in-magnitude gain modes
0 dB to 50 dB, for 0 V < V
DBS
< 1.5 V (30 mV/dB)
Inverted gain mode: 50 dB to 0 dB at −30 mV/dB
×0.03 to ×10 nominal gain for 15 mV < V
MAG
< 5 V
Constant bandwidth: 150 MHz at all gains
Low noise: 5 nV/√Hz typical at maximum gain
Low distortion: ≤−62 dBc typical
Low power: 20 mA typical at V
S
of 2.7 V to 6 V
Available in a space-saving, 3 mm × 3 mm LFCSP package
Low Cost, DC to 150 MHz,
Variable Gain Amplifier
AD8330
FUNCTIONAL BLOCK DIAGRAM
ENBL
OFST CNTR
CM AND
OFFSET
CONTROL
OPHI
OPLO
GAIN INTERFACE
OUTPUT
CONTROL
CMOP
03217-101
BIAS AND V
REF
INHI
VGA CORE
INLO
MODE
OUTPUT
STAGES
VDBS CMGN COMM
VMAG
Figure 1.
APPLICATIONS
Pre-ADC signal conditioning
75 Ω cable driving adjust
AGC amplifiers
GENERAL DESCRIPTION
The
AD8330
is a wideband variable gain amplifier for applications
requiring a fully differential signal path, low noise, well-defined
gain, and moderately low distortion, from dc to 150 MHz. The
input pins can also be driven from a single-ended source. The
peak differential input is ±2 V, allowing sine wave operation at
1 V rms with generous headroom. The output pins can drive
single-sided loads essentially rail-to-rail. The differential output
resistance is 150 Ω. The output swing is a linear function of the
voltage applied to the VMAG pin that internally defaults to 0.5 V,
providing a peak output of ±2 V. This can be raised to 10 V p-p,
limited by the supply voltage.
The basic gain function is linear-in-dB, controlled by the voltage
applied to Pin VDBS. The gain ranges from 0 dB to 50 dB for
control voltages between 0 V and 1.5 V—a slope of 30 mV/dB.
The gain linearity is typically within ±0.1 dB. By changing the
logic level on Pin MODE, the gain decreases over the same range,
with an opposite slope. A second gain control port is provided
at the VMAG pin and allows the user to vary the numeric gain
from a factor of 0.03 to 10. All the parameters of the
AD8330
have low sensitivities to temperature and supply voltages. Using
VMAG, the basic 0 dB to 50 dB range can be repositioned to
any value from 20 dB higher (that is, 20 dB to 70 dB) to at least
30 dB lower (that is, –30 dB to +20 dB) to suit the application,
thereby providing an unprecedented gain range of over 100 dB.
A unique aspect of the AD8330 is that its bandwidth and pulse
response are essentially constant for all gains, over both the
basic 50 dB linear-in-dB range, but also when using the linear-
in-magnitude function. The exceptional stability of the HF
response over the gain range is of particular value in those VGA
applications where it is essential to maintain accurate gain law-
conformance at high frequencies.
An external capacitor at Pin OFST sets the high-pass corner of
an offset reduction loop, whose frequency can be as low as 5 Hz.
When this pin is grounded, the signal path becomes dc-coupled.
When used to drive an ADC, an external common-mode control
voltage at Pin CNTR can be driven to within 0.5 V of either ground
or V
S
to accommodate a wide variety of requirements. By default,
the two outputs are positioned at the midpoint of the supply, V
S
/2.
Other features, such as two levels of power-down (fully off and
a hibernate mode), further extend the practical value of this
exceptionally versatile VGA.
The
AD8330
is available in 16-lead LFCSP and 16-lead QSOP
packages and is specified for operation from −40°C to +85°C.
Rev. H
Document Feedback
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2002–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
AD8330
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 15
Circuit Description..................................................................... 15
Using the AD8330 ...................................................................... 21
Data Sheet
Applications Information .............................................................. 26
ADC Driving............................................................................... 26
Simple AGC Amplifier .............................................................. 26
Wide Range True RMS Voltmeter............................................ 27
Evaluation Board ............................................................................ 29
General Description ................................................................... 29
Basic Operation .......................................................................... 29
Options ........................................................................................ 30
Measurement Setup.................................................................... 30
AD8330-EVALZ Board Design................................................. 30
Outline Dimensions ....................................................................... 32
Ordering Guide .......................................................................... 32
REVISION HISTORY
5/2016—Rev. G to Rev. H
Changes to Figure 2 and Table 3 ..................................................... 6
Moved Figure 3 ................................................................................. 7
Changes to Table 4 ............................................................................ 7
Change to Figure 45 ....................................................................... 15
Changes to Simple AGC Amplifier Section ................................ 27
Updated Outline Dimensions ....................................................... 32
Changes to Ordering Guide .......................................................... 32
5/2014—Rev. F to Rev. G
Changes to Table 1 ............................................................................ 3
11/2012—Rev. E to Rev. F
Changes to Figure 1 .......................................................................... 1
Changes to Output (Input) Common-Mode Control ............... 20
Updated Outline Dimensions ....................................................... 31
Changes to Ordering Guide .......................................................... 31
3/2010—Rev. D to Rev. E
Changes to Figure 2 and Table 3 ..................................................... 6
Changes to Figure 69 ...................................................................... 28
Changes to Figure 71 ...................................................................... 29
Changes to Figure 72 ...................................................................... 30
Deleted Table 7; Renumbered Sequentially ................................ 31
Changes to Ordering Guide .......................................................... 32
1/2008—Rev. C to Rev. D
Changes to Figure 28 and Figure 29............................................. 12
Added Evaluation Board Section ................................................. 28
Changes to Ordering Guide .......................................................... 33
6/2006—Rev. B to Rev. C
Updated Format .................................................................. Universal
Changes to Figure 1 ...........................................................................1
Deleted Figure 2; Renumbered Sequentially .................................1
Changes to Specifications Section ...................................................3
Change to Absolute Maximum Ratings .........................................5
Changes to Typical Performance Characteristics Summary
Statement ............................................................................................7
Changes to Figure 14 and Figure 15................................................8
Changes to Figure 31 and Figure 32............................................. 11
Updated Outline Dimensions ....................................................... 28
10/2004—Rev. A to Rev. B
Changes to Absolute Maximum Ratings Section and Ordering
Guide Section .....................................................................................4
Change to TPC 14 .............................................................................8
Note Added to CP-16 Package ...................................................... 26
4/2003—Rev. 0 to Rev. A
Updated Outline Dimensions ....................................................... 26
10/2002—Revision 0: Initial Version
Rev. H | Page 2 of 32
Data Sheet
SPECIFICATIONS
AD8330
V
S
= 5 V, T
A
= 25°C, C
L
= 12 pF on OPHI and OPLO, R
L
= ∞, V
DBS
= 0.75 V, V
MODE
= high, V
MAG
= Pin VMAG open circuit (0.5 V),
V
OFST
= 0 V, differential operation, unless otherwise noted.
Table 1.
Parameter
INPUT INTERFACE
Full-Scale Input
Input Resistance
Input Capacitance
Voltage Noise Spectral Density
Common-Mode Voltage Level
Input Offset
Drift
Permissible CM Range
1
Common-Mode AC Rejection
OUTPUT INTERFACE
Small Signal –3 dB Bandwidth
Peak Slew Rate
Peak-to-Peak Output Swing
Common-Mode Voltage
Offset Voltage
Offset Correction Enabled
Offset Correction Disabled
Voltage Noise Spectral Density
Differential Output Impedance
HD2
2
HD3
2
OUTPUT OFFSET CONTROL
AC-Coupled Offset
High-Pass Corner Frequency
COMMON-MODE CONTROL
Usable Voltage Range
Input Resistance
DECIBEL GAIN CONTROL
Normal Voltage Range
Elevated Range
Gain Scaling
Gain Linearity Error
Absolute Gain Error
Bias Current
Incremental Resistance
Gain Settling Time to 0.5 dB Error
Mode Up/Down
Mode Up Logic Level
Mode Down Logic Level
Test Conditions/Comments
Pin INHI, Pin INLO
V
DBS
= 0 V, differential drive
V
DBS
= 1.5 V
Pin-to-pin
Either pin to COMM
f = 1 MHz, V
DBS
= 1.5 V; inputs ac-shorted
Pin OFST connected to Pin COMM
0
f = 1 MHz, 0.1 V rms
f = 50 MHz
Pin OPHI, Pin OPLO
0 V < V
DBS
< 1.5 V
V
DBS
= 0 V
V
MAG
≥ 2 V (peaks are supply limited)
Pin CNTR O/C
±1.8
±4
2.4
−60
−55
150
1500
±2
±4.5
2.5
1
8
62
150
−62
−53
10
100
0.5
From Pin CNTR to V
S
/2
VDBS, CMGN, and MODE pins
CMGN connected to COMM
CMGN O/C (V
CMGN
rises to 0.2 V)
Mode high or low
0.3 V ≤ V
DBS
≤ 1.2 V
V
DBS
= 0 V
Flows out of Pin VDBS
V
DBS
stepped from 0.05 V to 1.45 V or 1.45 V to 0.05 V
Pin MODE
Gain increases with V
DBS
, MODE = O/C
Gain decreases with V
DBS
4
0 to 1.5
0.2 to 1.7
30
±0.1
±0.5
100
100
250
4.5
Min
±1.4
±4.5
800
Typ
±2
±6.3
1k
4
5
3.0
1
2
Max
Unit
V
mV
Ω
pF
nV/√Hz
V
mV rms
µV/°C
V
dB
dB
MHz
V/µs
V
V
V
mV
mV
nV/√Hz
Ω
dBc
dBc
mV rms
kHz
V
kΩ
V
V
mV/dB
dB
dB
nA
MΩ
ns
V
V
1.2 k
2.75
3.25
V
S
±2.2
2.6
±5
±40
180
Pin OFST connected to ground
f = 1 MHz, V
DBS
= 0 V
Pin-to-pin
V
OUT
= 1 V p-p, f = 10 MHz, R
L
= 1 kΩ
V
OUT
= 1 V p-p, f = 10 MHz, R
L
= 1 kΩ
Pin OFST
C
HPF
on Pin OFST (0 V < V
DBS
< 1.5 V)
C
HPF
= 3.3 nF, from OFST to CNTR (scales as 1/C
HPF
)
Pin CNTR
120
27
−0.35
−2
33
+0.35
+2
1.5
0.5
Rev. H | Page 3 of 32
AD8330
Parameter
LINEAR GAIN INTERFACE
Peak Output Scaling, Gain vs. V
MAG
Gain Multiplication Factor vs. V
MAG
Usable Input Range
Default Voltage
Incremental Resistance
Bandwidth
CHIP ENABLE
Logic Voltage for Full Shutdown
Logic Voltage for Hibernate Mode
Logic Voltage for Full Operation
Current in Full Shutdown
Current in Hibernate Mode
Minimum Time Delay
3
POWER SUPPLY
Supply Voltage
Quiescent Current
1
2
Data Sheet
Test Conditions/Comments
Pin VMAG, Pin CMGN
See the Circuit Description section
Gain is nominal when V
MAG
= 0.5 V
V
MAG
O/C
For V
MAG
≥ 0.1 V
Pin ENBL
Output pins remain at CNTR
1.3
2.3
Min
3.8
0
0.48
Typ
4.0
×2
0.5
4
150
Max
4.2
5
0.52
Unit
V/V
V
V
kΩ
MHz
V
V
V
µA
mA
µs
V
mA
1.5
20
1.5
1.7
0.5
1.7
100
VPSI, VPOS, VPSO, COMM, and CMOP pins
2.7
V
DBS
= 0.75 V
20
6
27
The use of an input common-mode voltage significantly different from the internally set value is not recommended due to its effect on noise performance. See Figure 56.
See the Typical Performance Characteristics section for more detailed information on distortion in a variety of operating conditions.
3
For minimum sized coupling capacitors.
Rev. H | Page 4 of 32
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage
Power Dissipation
16-Lead QSOP Package
1
16-Lead LFCSP Package
Input Voltage at Any Pin
Storage Temperature Range
θ
JA
16-Lead QSOP Package
16-Lead LFCSP Package
θ
JC
16-Lead QSOP Package
Operating Temperature Range
Lead Temperature (Soldering 60 sec)
1
AD8330
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rating
6V
0.62 W
1.67 W
V
S
+ 200 mV
−65°C to +150°C
105.4°C/W
60°C/W
39°C/W
−40°C to +85°C
300°C
ESD CAUTION
4-layer JEDEC Board (252P).
Rev. H | Page 5 of 32
