Ultralow Noise VGAs with
Preamplifier and Programmable R
IN
AD8331/AD8332/AD8334
FEATURES
Ultralow noise preamplifier (preamp)
Voltage noise = 0.74 nV/√Hz
Current noise = 2.5 pA/√Hz
3 dB bandwidth
AD8331:
120 MHz
AD8332, AD8334:
100 MHz
Low power
AD8331: 125 mW/channel
AD8332, AD8334: 145 mW/channel
Wide gain range with programmable postamp
−4.5 dB to +43.5 dB in LO gain mode
7.5 dB to 55.5 dB in HI gain mode
Low output-referred noise: 48 nV/√Hz typical
Active input impedance matching
Optimized for 10-bit/12-bit ADCs
Selectable output clamping level
Single 5 V supply operation
AD8332 and AD8334 available in lead frame chip scale package
FUNCTIONAL BLOCK DIAGRAM
LON LOP VIP
VIN
VCM
V
MID
–
INH
19dB
48dB
ATTENUATOR
+
HILO
3.5dB OR 15.5dB
VOH
21dB
PA
VOL
CLAMP
RCLMP
LNA
LMD
VCM
BIAS
VGA BIAS AND
INTERPOLATOR
GAIN
CONTROL
INTERFACE
ENB
GAIN
Figure 1. Signal Path Block Diagram
60
50
40
GAIN (dB)
V
GAIN
= 1V
V
GAIN
= 0.8V
V
GAIN
= 0.6V
V
GAIN
= 0.4V
V
GAIN
= 0.2V
V
GAIN
= 0V
HI GAIN
MODE
30
20
10
0
–10
100k
APPLICATIONS
Ultrasound and sonar time-gain controls
High performance automatic gain control (AGC) systems
I/Q signal processing
High speed, dual ADC drivers
GENERAL DESCRIPTION
The AD8331/AD8332/AD8334 are single-, dual-, and quad-
channel, ultralow noise linear-in-dB, variable gain amplifiers
(VGAs). Optimized for ultrasound systems, they are usable as a
low noise variable gain element at frequencies up to 120 MHz.
Included in each channel are an ultralow noise preamp (LNA),
an X-AMP® VGA with 48 dB of gain range, and a selectable gain
postamp with adjustable output limiting. The LNA gain is 19 dB
with a single-ended input and differential outputs. Using a single
resistor, the LNA input impedance can be adjusted to match a
signal source without compromising noise performance.
The 48 dB gain range of the VGA makes these devices suitable
for a variety of applications. Excellent bandwidth uniformity is
maintained across the entire range. The gain control interface
provides precise linear-in-dB scaling of 50 dB/V for control
voltages between 40 mV and 1 V. Factory trim ensures excellent
part-to-part and channel-to-channel gain matching.
1M
10M
FREQUENCY (Hz)
100M
1G
Figure 2. Frequency Response vs. Gain
Differential signal paths result in superb second- and third-
order distortion performance and low crosstalk.
The low output-referred noise of the VGA is advantageous in
driving high speed differential ADCs. The gain of the postamp
can be pin selected to 3.5 dB or 15.5 dB to optimize gain range
and output noise for 12-bit or 10-bit converter applications. The
output can be limited to a user-selected clamping level, preventing
input overload to a subsequent ADC. An external resistor adjusts
the clamping level.
The operating temperature range is −40°C to +85°C. The
AD8331 is available in a 20-lead QSOP package, the AD8332 is
available in 28-lead TSSOP and 32-lead LFCSP packages, and
the AD8334 is available in a 64-lead LFCSP package.
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2010 Analog Devices, Inc. All rights reserved.
03199-002
03199-001
AD8331/AD8332/AD8334
AD8331/AD8332/AD8334
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 12
Test Circuits ..................................................................................... 20
Measurement Considerations ................................................... 20
Theory of Operation ...................................................................... 24
Overview...................................................................................... 24
Low Noise Amplifier (LNA) ..................................................... 25
Variable Gain Amplifier ............................................................ 27
Postamplifier ............................................................................... 28
Applications Information .............................................................. 30
LNA—External Components .................................................... 30
Driving ADCs ............................................................................. 32
Overload ...................................................................................... 32
Optional Input Overload Protection ....................................... 32
Layout, Grounding, and Bypassing .......................................... 33
Multiple Input Matching ........................................................... 33
Disabling the LNA ...................................................................... 33
Ultrasound TGC Application ................................................... 34
High Density Quad Layout ....................................................... 34
AD8331 Evaluation Board ............................................................ 39
General Description ................................................................... 39
User-Supplied Optional Components ..................................... 39
Measurement Setup.................................................................... 39
Board Layout ............................................................................... 39
AD8331 Evaluation Board Schematics .................................... 40
AD8331 Evaluation Board PCB Layers ................................... 42
AD8332 Evaluation Board ............................................................ 43
General Description ................................................................... 43
User-Supplied Optional Components ..................................... 43
Measurement Setup.................................................................... 43
Board Layout ............................................................................... 43
Evaluation Board Schematics ................................................... 44
AD8332 Evaluation Board PCB Layers ................................... 46
AD8334 Evaluation Board ............................................................ 47
General Description ................................................................... 47
Configuring the Input Impedance ........................................... 48
Measurement Setup.................................................................... 48
Board Layout ............................................................................... 48
Evaluation Board Schematics ................................................... 49
AD8334 Evaluation Board PCB Layers ................................... 51
Outline Dimensions ....................................................................... 53
Ordering Guide .......................................................................... 55
Deleted AD8331 Bill of Materials Section and Table 11;
Renumbered Sequentially ............................................................. 43
Changes to Figure 104 ................................................................... 43
Changes to Figure 106 ................................................................... 45
Changes to Figure 107 ................................................................... 46
Changes to Figure 113 ................................................................... 47
Changes to Figure 114 and Board Layout Section ..................... 48
Deleted AD8332 Bill of Materials Section and Table 13;
Renumbered Sequentially ............................................................. 48
Changes to Figure 115 ................................................................... 49
Changes to Figure 116 ................................................................... 50
Changes to Figure 117 to Figure 120 ........................................... 51
Changes to Figure 121 ................................................................... 52
Deleted AD8334 Bill of Materials Section and Table 15;
Renumbered Sequentially ............................................................. 54
REVISION HISTORY
10/10—Rev. F to Rev. G
Changes to Quiescent Current per Channel Parameter,
Table 1 ................................................................................................ 6
Changes to Pin 1, Table 3 ................................................................. 8
Changes to Pin 1 and Pin 28, Table 4 and Pin 4 and Pin 5,
Table 5 ................................................................................................ 9
Changes to Figure 6 and Table 6 ................................................... 10
Changes to Figure 33 ...................................................................... 16
Changes to Figure 64 ...................................................................... 22
Changes to Figure 70 ...................................................................... 24
Changes to Low Noise Amplifier (LNA) Section and
Figure 74 .......................................................................................... 25
Changes to Figure 94 ...................................................................... 38
Changes to General Descriptions Section, Figure 95 Caption,
Table 10, and Board Layout Section ............................................. 39
Changes to Figure 96 ...................................................................... 40
Changes to Figure 97 ...................................................................... 41
Changes to Figure 98 and Figure 103........................................... 42
Rev. G | Page 2 of 56
AD8331/AD8332/AD8334
4/08—Rev. E to Rev. F
Changed R
FB
to R
IZ
Throughout ..................................................... 4
Changes to Figure 1........................................................................... 1
Changes to Table 1, LNA and VGA Characteristics, Output
Offset Voltage, Conditions ............................................................... 4
Changes to Quiescent Current per Channel and Power Down
Current Parameters ........................................................................... 6
Changes to Table 2 ............................................................................ 7
Changes to Table 3, Pin 1 Description ........................................... 8
Changes to Table 4, Pin 1 and Pin 28 Descriptions ...................... 9
Changes to Table 5, Pin 4 and Pin 5 Descriptions ........................ 9
Changes to Table 6, Pin 2, Pin 15, and Pin 20 Descriptions ......10
Changes to Table 6, Pin 61 Description .......................................11
Changes to Typical Performance Characteristics Section,
Default Conditions ..........................................................................12
Changes to Figure 25 ......................................................................15
Changes to Figure 39 ......................................................................17
Changes to Figure 55 Through Figure 68 ...................................20
Changes to Theory of Operation, Overview Section .................24
Changes to Low Noise Amplifier Section and Figure 74 ...........25
Changes to Active Impedance Matching Section, Figure 75,
and Figure 77 ...................................................................................26
Changes to Figure 78 ......................................................................27
Changes to Equation 6, Table 7, Figure 81, and Figure 82 .........30
Changes to Figure 83 ......................................................................31
Changes to Figure 88 ......................................................................32
Switched Figure 89 and Figure 90 .................................................33
Changes to Figure 89 ......................................................................33
Changes to Ultrasound TGC Application Section......................34
Incorporated AD8331-EVAL Data Sheet, Rev. A .......................39
Changes to User-Supplied Optional Components Section
and Measurement Setup Section ...................................................39
Changes to Figure 95 ......................................................................39
Changes to Figure 97 ......................................................................41
Added Figure 98 ..............................................................................42
Incorporated AD8332-EVALZ Data Sheet, Rev. D.....................44
Incorporated AD8334-EVAL Data Sheet, Rev. 0 ........................49
Updated Outline Dimensions ........................................................55
Changes to Ordering Guide ...........................................................57
4/06—Rev. D to Rev. E
Added AD8334 ................................................................... Universal
Changes to Figure 1 and Figure 2.................................................... 1
Changes to Table 1 ............................................................................ 4
Changes to Table 2 ............................................................................ 7
Changes to Figure 7 through Figure 9 and Figure 12 .................12
Changes to Figure 13, Figure 14, Figure 16, and Figure 18 .......13
Changes to Figure 23 and Figure 24 ............................................. 14
Changes to Figure 25 through Figure 27...................................... 15
Changes to Figure 31 and Figure 33 through Figure 36 ............ 16
Changes to Figure 37 through Figure 42...................................... 17
Changes to Figure 43, Figure 44, and Figure 48 .......................... 18
Changes to Figure 49, Figure 50, and Figure 54 .......................... 19
Inserted Figure 56 and Figure 57 .................................................. 20
Inserted Figure 58, Figure 59, and Figure 61 ............................... 21
Changes to Figure 60 ...................................................................... 21
Inserted Figure 63 and Figure 65 .................................................. 22
Changes to Figure 64 ...................................................................... 22
Moved Measurement Considerations Section ............................ 23
Inserted Figure 67 and Figure 68 .................................................. 23
Inserted Figure 70 and Figure 71 .................................................. 24
Change to Figure 72 ........................................................................ 24
Changes to Figure 73 and Low Noise Amplifier Section ........... 25
Changes to Postamplifier Section ................................................. 28
Changes to Figure 80 ...................................................................... 29
Changes to LNA—External Components Section ...................... 30
Changes to Logic Inputs—ENB, MODE, and HILO Section ... 31
Changes to Output Decoupling and Overload Sections ............ 32
Changes to Layout, Grounding, and Bypassing Section ............ 33
Changes to Ultrasound TGC Application Section ..................... 34
Added High Density Quad Layout Section ................................. 34
Inserted Figure 94 ........................................................................... 38
Updated Outline Dimensions........................................................ 39
Changes to Ordering Guide ........................................................... 40
3/06—Rev. C to Rev. D
Updated Format ................................................................. Universal
Changes to Features and General Description .............................. 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 6
Changes to Ordering Guide ........................................................... 34
11/03—Rev. B to Rev. C
Addition of New Part ......................................................... Universal
Changes to Figures ............................................................. Universal
Updated Outline Dimensions........................................................ 32
5/03—Rev. A to Rev. B
Edits to Ordering Guide ................................................................. 32
Edits to Ultrasound TGC Application Section ........................... 25
Added Figure 71, Figure 72, and Figure 73.................................. 26
Updated Outline Dimensions........................................................ 31
2/03—Rev. 0 to Rev. A
Edits to Ordering Guide ................................................................. 32
Rev. G | Page 3 of 56
AD8331/AD8332/AD8334
SPECIFICATIONS
T
A
= 25°C, V
S
= 5 V, R
L
= 500 Ω, R
S
= R
IN
= 50 Ω, R
IZ
= 280 Ω, C
SH
= 22 pF, f = 10 MHz, R
CLMP
= ∞, C
L
= 1 pF, VCM pin floating,
−4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified.
Table 1.
Parameter
LNA CHARACTERISTICS
Gain
Input Voltage Range
Input Resistance
Test Conditions/Comments
Single-ended input to differential output
Input to output (single-ended)
AC-coupled
R
IZ
= 280 Ω
R
IZ
= 412 Ω
R
IZ
= 562 Ω
R
IZ
= 1.13 kΩ
R
IZ
= ∞
Single-ended, either output
V
OUT
= 0.2 V p-p
R
S
= 0 Ω, HI or LO gain, R
IZ
= ∞, f = 5 MHz
R
IZ
= ∞, HI or LO gain, f = 5 MHz
f = 10 MHz, LOP output
R
S
= R
IN
= 50 Ω
R
S
= 50 Ω, R
IZ
= ∞
V
OUT
= 0.5 V p-p, single-ended, f = 10 MHz
Min
Typ
19
13
±275
50
75
100
200
6
13
5
130
650
0.74
2.5
3.7
2.5
−56
−70
165
Max
Unit
1
dB
dB
mV
Ω
Ω
Ω
Ω
kΩ
pF
Ω
MHz
V/μs
nV/√Hz
pA/√Hz
dB
dB
dBc
dBc
mA
Input Capacitance
Output Impedance
−3 dB Small Signal Bandwidth
Slew Rate
Input Voltage Noise
Input Current Noise
Noise Figure
Active Termination Match
Unterminated
Harmonic Distortion at LOP1 or LOP2
HD2
HD3
Output Short-Circuit Current
LNA AND VGA CHARACTERISTICS
−3 dB Small Signal Bandwidth
AD8331
AD8332, AD8334
−3 dB Large Signal Bandwidth
AD8331
AD8332, AD8334
Slew Rate
AD8331
AD8332, AD8334
Input Voltage Noise
Noise Figure
Active Termination Match
Unterminated
Output-Referred Noise
AD8331
AD8332, AD8334
Output Impedance, Postamplifier
Pin LON, Pin LOP
V
OUT
= 0.2 V p-p
120
100
V
OUT
= 2 V p-p
110
90
LO gain
HI gain
LO gain
HI gain
R
S
= 0 Ω, HI or LO gain, R
IZ
= ∞, f = 5 MHz
V
GAIN
= 1.0 V
R
S
= R
IN
= 50 Ω, f = 10 MHz, measured
R
S
= R
IN
= 200 Ω, f = 5 MHz, simulated
R
S
= 50 Ω, R
IZ
= ∞, f = 10 MHz, measured
R
S
= 200 Ω, R
IZ
= ∞, f = 5 MHz, simulated
V
GAIN
= 0.5 V, LO gain
V
GAIN
= 0.5 V, HI gain
V
GAIN
= 0.5 V, LO gain
V
GAIN
= 0.5 V, HI gain
DC to 1 MHz
300
1200
275
1100
0.82
4.15
2.0
2.5
1.0
48
178
40
150
1
MHz
MHz
MHz
MHz
V/μs
V/μs
V/μs
V/μs
nV/√Hz
dB
dB
dB
dB
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
Ω
Rev. G | Page 4 of 56
AD8331/AD8332/AD8334
Parameter
Output Signal Range, Postamplifier
Differential
Output Offset Voltage
AD8331
AD8332, AD8334
Output Short-Circuit Current
Harmonic Distortion
AD8331
HD2
HD3
HD2
HD3
AD8332, AD8334
HD2
HD3
HD2
HD3
Input 1 dB Compression Point
Two-Tone Intermodulation Distortion (IMD3)
AD8331
AD8332, AD8334
Output Third-Order Intercept
AD8331
AD8332, AD8334
Channel-to-Channel Crosstalk (AD8332, AD8334)
Overload Recovery
Group Delay Variation
ACCURACY
Absolute Gain Error
2
Test Conditions/Comments
R
L
≥ 500 Ω, unclamped, either pin
Min
Typ
V
CM
± 1.125
4.5
±5
−25
±5
–25
45
Max
Unit
1
V
V p-p
mV
mV
mV
mV
mA
Differential, V
GAIN
= 0.5 V
Common mode
Differential, 0.05 V ≤ V
GAIN
≤ 1.0 V
Common mode
V
GAIN
= 0.5 V, V
OUT
= 1 V p-p, HI gain
f = 1 MHz
f = 10 MHz
−50
−125
−20
−125
+50
+100
+20
+100
−88
−85
−68
−65
−82
−85
−62
−66
1
−80
−72
−78
−74
38
33
35
32
−98
5
±2
−1
−1
−2
+0.5
±0.3
−1
±0.2
±0.1
50
−4.5 to +43.5
7.5 to 55.5
0 to 1.0
10
500
30
−25
1.5 to 3.5
+2
+1
+1
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm
dBc
dBc
dBc
dBc
dBm
dBm
dBm
dBm
dB
ns
ns
dB
dB
dB
dB
dB
dB/V
dB
dB
V
MΩ
ns
Ω
mV
V
f = 1 MHz
f = 10 MHz
V
GAIN
= 0.25 V, V
OUT
= 1 V p-p, f = 1 MHz to 10 MHz
V
GAIN
= 0.72 V, V
OUT
= 1 V p-p, f = 1 MHz
V
GAIN
= 0.5 V, V
OUT
= 1 V p-p, f = 10 MHz
V
GAIN
= 0.72 V, V
OUT
= 1 V p-p, f = 1 MHz
V
GAIN
= 0.5 V, V
OUT
= 1 V p-p, f = 10 MHz
V
GAIN
= 0.5 V, V
OUT
= 1 V p-p, f = 1 MHz
V
GAIN
= 0.5 V, V
OUT
= 1 V p-p, f = 10 MHz
V
GAIN
= 0.5 V, V
OUT
= 1 V p-p, f = 1 MHz
V
GAIN
= 0.5 V, V
OUT
= 1 V p-p, f = 10 MHz
V
GAIN
= 0.5 V, V
OUT
= 1 V p-p, f = 1 MHz
V
GAIN
= 1.0 V, V
IN
= 50 mV p-p/1 V p-p, f = 10 MHz
5 MHz < f < 50 MHz, full gain range
0.05 V < V
GAIN
< 0.10 V
0.10 V < V
GAIN
< 0.95 V
0.95 V < V
GAIN
< 1.0 V
0.1 V < V
GAIN
< 0.95 V
0.1 V < V
GAIN
< 0.95 V
0.10 V < V
GAIN
< 0.95 V
LO gain
HI gain
Gain Law Conformance
3
Channel-to-Channel Gain Matching
GAIN CONTROL INTERFACE (Pin GAIN)
Gain Scaling Factor
Gain Range
Input Voltage (V
GAIN
) Range
Input Impedance
Response Time
COMMON-MODE INTERFACE (PIN VCMx)
Input Resistance
4
Output CM Offset Voltage
Voltage Range
48.5
51.5
48 dB gain change to 90% full scale
Current limited to ±1 mA
V
CM
= 2.5 V
V
OUT
= 2.0 V p-p
−125
+100
Rev. G | Page 5 of 56
