Data Sheet
FEATURES
16-Bit, 20/40/65/80 MSPS,
1.8 V Dual Analog-to-Digital Converter
AD9269
FUNCTIONAL BLOCK DIAGRAM
AVDD
GND
SDIO SCLK CSB
SPI
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Integrated quadrature error correction (QEC)
SNR
77.6 dBFS at 9.7 MHz input
71 dBFS at 200 MHz input
SFDR
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input
Low power
44 mW per channel at 20 MSPS
100 mW per channel at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = −0.5/+1.1 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer (DCS)
Integer 1-to-6 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock output (DCO) with programmable clock and
data alignment
AD9269
VIN+A
ADC
VIN–A
PROGRAMMING DATA
CMOS
OUTPUT BUFFER
ORA
D15A
D0A
DCOA
VREF
SENSE
VCM
RBIAS
VIN–B
ADC
VIN+B
REF
SELECT
QUADRATURE
ERROR
CORRECTION
MUX OPTION
DRVDD
CMOS
OUTPUT BUFFER
ORB
D15B
D0B
DCOB
DIVIDE
1 TO 6
DUTY CYCLE
STABILIZER
MODE
CONTROLS
08538-001
CLK+ CLK–
SYNC
DCS
PDWN DFS OEB
Figure 1.
PRODUCT HIGHLIGHTS
1.
The AD9269 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
The patented sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
An optional SPI selectable dc correction and quadrature
error correction (QEC) feature corrects for dc offset, gain,
and phase mismatches between the two channels.
A standard serial port interface (SPI) supports various
product features and functions, such as data output format-
ting, internal clock divider, power-down, DCO/data timing
and offset adjustments, and voltage reference modes.
The AD9269 is packaged in a 64-lead RoHS-compliant
LFCSP that is pin compatible with the
AD9268
16-bit
ADC, the
AD9258
14-bit ADC, the
AD9251
14-bit ADC
the
AD9231
12-bit ADC, the
AD6659
12-bit baseband
diversity receiver, and the
AD9204
10-bit ADC, enabling a
simple migration path between 10-bit and 16-bit converters
sampling from 20 MSPS to 125 MSPS.
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
2.
3.
4.
5.
Rev. A
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AD9269
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications.......................................................................... 6
Digital Specifications ................................................................... 7
Switching Specifications .............................................................. 8
Timing Specifications .................................................................. 9
Absolute Maximum Ratings.......................................................... 10
Thermal Characteristics ............................................................ 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 13
AD9269-80 .................................................................................. 13
AD9269-65 .................................................................................. 15
AD9269-40 .................................................................................. 16
AD9269-20 .................................................................................. 17
Equivalent Circuits ......................................................................... 18
Theory of Operation ...................................................................... 19
ADC Architecture ...................................................................... 19
Analog Input Considerations.................................................... 19
Voltage Reference ....................................................................... 21
Data Sheet
Clock Input Considerations ...................................................... 22
Power Dissipation and Standby Mode .................................... 24
Digital Outputs ........................................................................... 25
Timing ......................................................................................... 25
Built-In Self-Test (BIST) and Output Test .................................. 26
Built-In Self-Test (BIST) ............................................................ 26
Output Test Modes ..................................................................... 26
Channel/Chip Synchronization .................................................... 27
DC and Quadrature Error Correction (QEC) ............................ 28
Serial Port Interface (SPI) .............................................................. 29
Configuration Using the SPI ..................................................... 29
Hardware Interface..................................................................... 29
Configuration Without the SPI ................................................ 30
SPI Accessible Features .............................................................. 30
Memory Map .................................................................................. 31
Reading the Memory Map Register Table............................... 31
Open Locations .......................................................................... 31
Default Values ............................................................................. 31
Memory Map Register Table ..................................................... 32
Memory Map Register Descriptions ........................................ 34
Applications Information .............................................................. 36
Design Guidelines ...................................................................... 36
Outline Dimensions ....................................................................... 37
Ordering Guide .......................................................................... 37
REVISION HISTORY
8/2016—Rev. 0 to Rev. A
Changes to Figure 3 ................................................................................. 8
Updated Outline Dimensions ............................................................... 37
1/2010—Revision 0: Initial Version
Rev. A | Page 2 of 40
Data Sheet
GENERAL DESCRIPTION
The AD9269 is a monolithic, dual-channel, 1.8 V supply, 16-bit,
20/40/65/80 MSPS analog-to-digital converter (ADC). It features
a high performance sample-and-hold circuit and on-chip voltage
reference.
The product uses multistage differential pipeline architecture with
output error correction logic to provide 16-bit accuracy at 80 MSPS
data rates and to guarantee no missing codes over the full operating
temperature range.
The AD9269 incorporates an optional integrated dc correction
and quadrature error correction block (QEC) that corrects for
dc offset, gain, and phase mismatch between the two channels.
This functional block can be very beneficial to complex signal
processing applications such as direct conversion receivers.
The ADC also contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
AD9269
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom
user-defined test patterns entered via the serial port interface (SPI).
A differential clock input controls all internal conversion cycles.
An optional duty cycle stabilizer (DCS) compensates for wide
variations in the clock duty cycle while maintaining excellent
overall ADC performance.
The digital output data is presented in offset binary, gray code,
or twos complement format. A data output clock (DCO) is pro-
vided for each ADC channel to ensure proper latch timing with
receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported,
and output data can be multiplexed onto a single output bus.
The AD9269 is available in a 64-lead RoHS-compliant LFCSP
and is specified over the industrial temperature range (−40°C to
+85°C).
Rev. A | Page 3 of 40
AD9269
SPECIFICATIONS
DC SPECIFICATIONS
Data Sheet
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
1
Differential
Nonlinearity
(DNL)
2
Integral Nonlinearity
(INL)
2
MATCHING
CHARACTERISTICS
Offset Error
Gain Error
1
TEMPERATURE DRIFT
Offset Error
INTERNAL VOLTAGE
REFERENCE
Output Voltage
(1 V Mode)
Load Regulation
Error at 1.0 mA
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span,
VREF = 1.0 V
Input Capacitance
3
Input Common-
Mode Voltage
Input Common-
Mode Range
REFERENCE INPUT
RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD
2
IDRVDD
2
(1.8 V)
IDRVDD
2
(3.3 V)
Temp
Full
Full
Full
Full
Full
25°C
Full
25°C
AD9269-20/AD9269-40
Min
Typ
Max
16
Guaranteed
±0.05
±0.40
−2.0
−0.9/+1.2
−0.5/+0.6
±5.50
±2.0
±2.2
Min
16
AD9269-65
Typ
Max
Min
16
AD9269-80
Typ
Max
Unit
Bits
Guaranteed
±0.05
±0.50
−2.0
−0.9/+1.4
−0.5/+1.1
±6.50
Guaranteed
±0.05
±0.50
−2.0
−0.9/+1.65
−0.5/+1.1
±6.50
±3.3
% FSR
% FSR
LSB
LSB
LSB
LSB
25°C
25°C
Full
±0.0
±0.2
±2
±0.50
±0.0
±0.2
±2
±0.55
±0.0
±0.2
±2
±0.65
% FSR
% FSR
ppm/°C
Full
Full
0.981
0.993
2
1.005
0.981
0.993
2
1.005
0.981
0.993
2
1.005
V
mV
25°C
2.8
2.8
2.8
LSB
rms
V p-p
pF
V
1.3
V
kΩ
Full
Full
Full
Full
Full
0.5
2
6.5
0.9
1.3
7.5
0.5
2
6.5
0.9
1.3
7.5
0.5
2
6.5
0.9
7.5
Full
Full
Full
Full
Full
1.7
1.7
1.8
1.9
3.6
52.5/72.6
1.7
1.7
1.8
1.9
3.6
101.2
1.7
1.7
1.8
1.9
3.6
119
V
V
mA
mA
mA
50.0/69.3
3.9/6.4
7.4/12.4
96.6
9.6
18.7
113
11.8
23
Rev. A | Page 4 of 40
Data Sheet
Parameter
POWER
CONSUMPTION
DC Input
Sine Wave Input
2
(DRVDD = 1.8 V)
Sine Wave Input
2
(DRVDD = 3.3 V)
Standby Power
4
Power-Down Power
1
2
AD9269
Temp
AD9269-20/AD9269-40
Min
Typ
Max
Min
AD9269-65
Typ
Max
Min
AD9269-80
Typ
Max
Unit
Full
Full
Full
Full
Full
87.7/121.7
96.9/136.3
114.4/165.7
37/37
1.0
102.0/142.3
170.7
191.2
235.6
37
1.0
199.8
200
224.6
279
37
1.0
240
mW
mW
mW
mW
mW
Measured with a 1.0 V external reference.
Measured with a 10 MHz input frequency at a rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
4
Standby power is measured with a dc input and the CLK+, CLK− active.
Rev. A | Page 5 of 40
