Preliminary Technical Data
FEATURES
1
0
8-, 10-, 12-, 14-Bit, 175 MSPS
TxDAC
®
D/A Converters
AD9704/AD9705/AD9706/AD9707
FUNCTIONAL BLOCK DIAGRAMS
Pin-compatible Family
Low Power Member of Pin Compatible
TxDAC Product Family
Power Dissipation @ 3.3 V:
21 mW @ 10 MSPS
24 mW @ 25 MSPS
30 mW @ 50 MSPS
Sleep Mode: 5 mW @ 3.3 V
Supply Voltage: 1.7 V to 3.6 V
SFDR to Nyquist:
AD9707: 85 dBc @ 5 MHz Output
AD9707: 80 dBc @ 10 MHz Output
AD9707: 75 dBc @ 20 MHz Output
AD9707 SNR @ 10 MHz Output, 125 MSPS: TBD dB
Differential Current Outputs: 1 mA to 5 mA
Data Format: Twos Complement or Straight Binary
On-Chip 1.0 V Reference
CMOS Compatible Digital Interface
Edge-Triggered Latches
Figure 1. AD9707 Functional Block Diagram (LFCSP Package)
32-LEAD LFCSP PACKAGE FEATURES
Clock Input: Single-Ended and Differential
Output Common Mode: Adjustable 0 V to 1.2 V
Power-Down Mode: < 400
μW
@ 3.3 V (SPI Controllable)
Serial Peripheral Interface (SPI)
Self-calibration
32-Lead LFCSP Pb-Free Package
Figure 2. AD9707 Functional Block Diagram (TSSOP Package)
28-LEAD TSSOP PACKAGE FEATURES
Internal 500Ω Load Resistor
Internal 16kΩ Resistor to Set Full Scale Current Output
Clock Input: Single-Ended
28-Lead TSSOP Pb-Free Package
1
Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519
Rev. PrC
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© 2006 Analog Devices, Inc. All rights reserved.
AD9704/AD9705/AD9706/AD9707
GENERAL DESCRIPTION
The AD9704/05/06/07 are the fourth generation family in the
TxDAC series of high performance, CMOS digital-to-analog
converters (DACs). This pin compatible 8–/10–/12–/14–bit
resolution family has been optimized for low power operation
while maintaining excellent dynamic performance. The AD970x
family is pin compatible with the AD9748/40/42/44 family of
TxDAC converters and is specifically optimized for the transmit
signal path of communication systems. All of the devices share
the same interface, small outline package, and pinout, providing
an upward or downward component selection path based on
performance, resolution, and cost. The AD970X offers
exceptional ac and dc performance while supporting update
rates up to 175 MSPS.
The AD970X’s flexible power supply operating range of 1.7 V to
3.6 V and low power dissipation makes it well suited for
portable and low power applications. Its power dissipation can
be further reduced to 15 mW with a slight degradation in
performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 5 mW.
The AD970X-LFCSP has an optional serial peripheral interface
(SPI) which provides a higher level of programmability to
enhance performance of the DAC. An adjustable output
common mode feature has also been added to the AD970X-
LFCSP that allows for easy interfacing to other components that
require common modes greater than 0 V.
Edge-triggered input latches and a 1.0 V temperature
Preliminary Technical Data
compensated band gap reference have been integrated to
provide a complete monolithic DAC solution. The digital inputs
support 1.8 V and 3.3 V CMOS logic families.
PRODUCT HIGHLIGHTS
1.
2.
Pin Compatible: The AD970x line of TxDACs is pin
compatible with the AD974x TxDAC line.
Low power: Complete CMOS DAC operates on a single
supply of 3.6 V down to 1.7 V, consuming 25mW (3.3V)
and 10mW (1.8 V). The DAC full-scale current can be
reduced for lower power operation, and sleep and
power-down modes are provided for low power idle
periods.
Self-Calibration (foreground) enables true 14-bit INL
and DNL performance. (LFCSP only)
Data input supports twos complement or straight binary
data coding.
High speed, single-ended and differential (LFCSP only)
CMOS clock input supports 175 MSPS conversion rate.
SPI control offers higher level of programmability.
(LFCSP package only)
Adjustable output common mode from 0 V to 1.2 V
allows for easy interfacing to other components that
accept common mode levels greater than 0 V (LFCSP
only).
On-chip voltage reference: The AD970X includes a 1.0 V
temperature compensated band gap voltage reference.
Industry-standard 28-lead TSSOP and 32-lead LFCSP
packages.
3.
4.
5.
6.
7.
8.
9.
Rev. PrC | Page 2 of 32
Preliminary Technical Data
TABLE OF CONTENTS
0
H
AD9704/AD9705/AD9706/AD9707
FEATURES ................................................................................... 1
3 7
H
1 9
H
Functional Description ................................................................. 21
5 6
H
2 0
H
1
H
32-LEAD LFCSP PACKAGE FEATURES................................ 1
3 8
H
Serial Peripheral Interface (LFCSP only) ............................... 21
5 7
H
2
H
28-LEAD TSSOP PACKAGE FEATURES ............................... 1
3 9
H
2 1
H
SPI Register Map ....................................................................... 23
5 8
H
3
H
FUNCTIONAL BLOCK DIAGRAMS...................................... 1
4 0
H
2 2
H
SPI Register Descriptions ......................................................... 23
5 9
H
4
H
GENERAL DESCRIPTION ....................................................... 2
4 1
H
2 3
H
Reference Operation ................................................................. 24
6 0
H
5
H
PRODUCT HIGHLIGHTS ........................................................ 2
4 2
H
4 3
H
2 4
H
Reference Control Amplifier.................................................... 24
6 1
H
6
H
AD9704/05/06/07–Specifications .................................................. 4
7
H
2 5
H
DAC Transfer Function ............................................................ 24
6 2
H
DC Specifications (3.3 V) ........................................................... 4
4 4
H
2 6
H
Analog Outputs.......................................................................... 25
6 3
H
8
H
Dynamic Specifications (3.3V) .................................................. 6
4 5
H
2 7
H
Adjustable Output Common Mode (LFCSP only) ............... 26
6 4
H
9
H
Digital Specifications (3.3V) ...................................................... 7
4 6
H
2 8
H
Digital Inputs ............................................................................. 26
6 5
H
1 0
H
DC Specifications (1.8V) ............................................................ 8
4 7
H
2 9
H
Clock Input................................................................................. 26
6 6
H
1 1
H
Dynamic Specifications (1.8V) ................................................ 10
4 8
H
3 0
H
DAC Timing............................................................................... 26
6 7
H
1 2
H
Digital Specifications (1.8V) .................................................... 11
4 9
H
5 0
H
3 2
H
3 1
H
Power Dissipation...................................................................... 27
6 8
H
6 9
H
1 3
H
Absolute Maximum Ratings......................................................... 12
1 4
H
Evaluation Board ........................................................................... 29
3 3
H
Thermal Characteristics ........................................................... 12
5 1
H
General Description .................................................................. 29
7 0
H
7 1
H
1 5
H
ESD Caution............................................................................... 12
5 2
H
5 3
H
3 4
H
Outline Dimensions ...................................................................... 30
Ordering Guide.............................................................................. 31
7 2
H
1 6
H
Pin Configuration and Function Descriptions .......................... 13
Definitions of Specifications ........................................................ 17
5 4
H
3 5
H
1 7
H
3 6
H
Revision History ............................................................................ 32
7 3
H
1 8
H
AD9707–Typical Performance Characteristics ......................... 18
5 5
H
Rev. PrC | Page 3 of 32
AD9704/AD9705/AD9706/AD9707
AD9704/05/06/07–SPECIFICATIONS
DC SPECIFICATIONS (3.3 V)
Preliminary Technical Data
(T
MIN
to T
MAX
, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
OUTFS
= 2 mA, unless otherwise noted.)
Table 1.
Parameter
RESOLUTION
DC ACCURACY
1
Integral Nonlinearity (INL) Pre-
calibration
Integral Nonlinearity (INL) Post-
calibration
2
Differential Nonlinearity (DNL) Pre-
calibration
Differential Nonlinearity (DNL)
Post-calibration
2
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal
Reference)
Gain Error (With Internal
Reference)
Full-Scale Output Current
3
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current
4
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance (Ext.
Reference)
Small Signal Bandwidth
TEMPERATURE COEFFICIENTS
Offset Drift
0
F
1
F
2
F
3
F
AD9707
Min Typ Max
AD9706
Min Typ Max
AD9705
Min Typ Max
AD9704
Min Typ Max
14
TBD
TBD
TBD
TBD
Unit
Bits
LSB
LSB
LSB
LSB
±3
±0.8
±1.5
±0.7
±0.5
±0.25
±0.25
±0.13
±0.12
±0.04
±0.07
±0.03
-0.02
+0.02 -0.02
+0.02
-0.02
+0.02
-0.02
+0.02
% of FSR
% of FSR
% of FSR
mA
V
MΩ
pF
V
nA
-0.8
1
-1
-0.2
2
200
5
1.0
100
+0.2
-0.8
-0.2
2
200
5
1.0
100
+0.2
5
+1.25
-0.8
1
-1
-0.2
2
200
5
1.0
100
+0.2
5
+1.25
-0.8
1
-1
-0.2
2
200
5
1.0
100
+0.2
5
+1.25
5
1
+1.25 -1
0.1
1
0.5
0
TBD
± 70
± 80
1.25
0.1
1
0.5
0
TBD
± 70
± 80
1.25
0.1
1
0.5
0
TBD
± 70
± 80
1.25
0.1
1
0.5
0
TBD
± 70
± 80
1.25
V
MΩ
MHz
ppm of
FSR/°C
ppm of
FSR/°C
ppm of
FSR/°C
ppm/°C
Gain Drift (Without Internal
Reference)
Gain Drift (With Internal
Reference)
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
AVDD
DVDD
CLKVDD
Analog Supply Current (I
AVDD
)
Digital Supply Current (I
DVDD
)
5
Clock Supply Current (I
CLKVDD
)
Supply Current Sleep Mode (I
AVDD
)
Supply Current Power-Down
Mode
4
F
2.5
2.5
2.5
3.3
3.3
3.3
4.5
1.1
1.7
0.4
20
3.6
3.6
3.6
2.5
2.5
2.5
1.0
3.3
3.3
3.3
4.5
1.1
1.7
0.4
20
3.6
3.6
3.6
2.5
2.5
2.5
1.0
3.3
3.3
3.3
4.5
1.1
1.7
0.4
20
3.6
3.6
3.6
2.5
2.5
2.5
1.0
3.3
3.3
3.3
4.5
1.1
1.7
0.4
20
3.6
3.6
3.6
1.0
V
V
V
mA
mA
mA
mA
μA
Rev. PrC | Page 4 of 32
Preliminary Technical Data
Power Dissipation
5
Power Dissipation
6
Power Supply Rejection Ratio—
AVDD
7
Power Supply Rejection Ratio—
DVDD
7
OPERATING RANGE
7 4
H
5
F
6
F
75
H
AD9704/AD9705/AD9706/AD9707
24
46
24
46
+1
-1
+1
+0.04
+85
-1
-0.04
-40
24
46
+1
+0.04
+85
-1
-0.04
-40
24
46
+1
+0.04
+85
mW
mW
% of
FSR/V
% of
FSR/V
°C
-1
-0.04
-40
+0.04 -0.04
+85
-40
1
2
Measured at IOUTA, driving a virtual ground.
Calibration offered in LFCSP package only.
3
Nominal full-scale current, I
OUTFS
, is 32 times the I
REF
current.
4
An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
5
Measured at f
CLOCK
= 25 MSPS and f
OUT
= 2.5 MHz.
6
Measured at f
CLOCK
= 175 MSPS and f
OUT
= 20 MHz.
7
±5% power supply variation.
Rev. PrC | Page 5 of 32
