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20 mW Power, 2.3 V to 5.5 V,
75 MHz Complete DDS
AD9834
FEATURES
Narrow-band SFDR >72 dB
2.3 V to 5.5 V power supply
Output frequency up to 37.5 MHz
Sine output/triangular output
On-board comparator
3-wire SPI® interface
Extended temperature range: −40°C to +105°C
Power-down option
20 mW power consumption at 3 V
20-lead TSSOP
Capability for phase modulation and frequency modulation is
provided. The frequency registers are 28 bits; with a 75 MHz clock
rate, resolution of 0.28 Hz can be achieved. Similarly, with a 1 MHz
clock rate, the AD9834 can be tuned to 0.004 Hz resolution.
Frequency and phase modulation are affected by loading registers
through the serial interface and toggling the registers using
software or the FSELECT pin and PSELECT pin, respectively.
The AD9834 is written to using a 3-wire serial interface. This
serial interface operates at clock rates up to 40 MHz and is
compatible with DSP and microcontroller standards.
The device operates with a power supply from 2.3 V to 5.5 V.
The analog and digital sections are independent and can be run
from different power supplies, for example, AVDD can equal
5 V with DVDD equal to 3 V.
The AD9834 has a power-down pin (SLEEP) that allows
external control of the power-down mode. Sections of the
device that are not being used can be powered down to
minimize the current consumption. For example, the DAC can
be powered down when a clock output is being generated.
The part is available in a 20-lead TSSOP.
APPLICATIONS
Frequency stimulus/waveform generation
Frequency phase tuning and modulation
Low power RF/communications systems
Liquid and gas flow measurement
Sensory applications: proximity, motion, and defect
detection
Test and medical equipment
GENERAL DESCRIPTION
The AD9834 is a 75 MHz low power DDS device capable of
producing high performance sine and triangular outputs. It also
has an on-board comparator that allows a square wave to be
produced for clock generation. Consuming only 20 mW of power
at 3 V makes the AD9834 an ideal candidate for power-sensitive
applications.
AVDD
AGND
DGND
DVDD
CAP/2.5V
FUNCTIONAL BLOCK DIAGRAM
REFOUT
ON-BOARD
REFERENCE
FULL-SCALE
CONTROL
COMP
FS ADJUST
REGULATOR
VCC
2.5V
28-BIT FREQ0
REG
MUX
28-BIT FREQ1
REG
MCLK
FSELECT
PHASE
ACCUMULATOR
(28-BIT)
Σ
12
SIN
ROM
MUX
10-BIT
DAC
IOUT
IOUTB
MSB
12-BIT PHASE0 REG
12-BIT PHASE1 REG
MUX
MUX
DIVIDED
BY 2
16-BIT CONTROL
REGISTER
SERIAL INTERFACE
AND
CONTROL LOGIC
MUX
SIGN BIT OUT
COMPARATOR
VIN
AD9834
FSYNC
SCLK
SDATA
PSELECT
SLEEP RESET
02705-001
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2011 Analog Devices, Inc. All rights reserved.
AD9834
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
Circuit Description......................................................................... 16
Numerically Controlled Oscillator Plus Phase Modulator ... 16
SIN ROM ..................................................................................... 16
Digital-to-Analog Converter (DAC) ....................................... 16
Comparator ................................................................................. 16
Regulator...................................................................................... 17
Output Voltage Compliance...................................................... 17
Functional Description .................................................................. 18
Serial Interface ............................................................................ 18
Powering Up the AD9834 ......................................................... 18
Latency......................................................................................... 18
Control Register ......................................................................... 18
Frequency and Phase Registers ................................................ 20
Writing to a Frequency Register............................................... 21
Writing to a Phase Register....................................................... 21
RESET Function ......................................................................... 21
SLEEP Function.......................................................................... 21
SIGN BIT OUT Pin.................................................................... 22
The IOUT and IOUTB Pins...................................................... 22
Applications Information .............................................................. 23
Grounding and Layout .................................................................. 26
Interfacing to Microprocessors..................................................... 27
AD9834 to ADSP-21xx Interface ............................................. 27
AD9834 to 68HC11/68L11 Interface....................................... 27
AD9834 to 80C51/80L51 Interface .......................................... 28
AD9834 to DSP56002 Interface ............................................... 28
Evaluation Board ............................................................................ 29
System Development Platform................................................. 29
AD9834 to SPORT Interface..................................................... 29
XO vs. External Clock................................................................ 29
Power Supply............................................................................... 29
Evaluation Board Schematics ................................................... 30
Evaluation Board Layout........................................................... 32
Outline Dimensions ....................................................................... 35
Ordering Guide .......................................................................... 35
Rev. C | Page 2 of 36
AD9834
REVISION HISTORY
2/11—Rev. B to Rev. C
Changes to I
DD
Parameter, Table 1 ..................................................5
Changes to FS ADJUST Description, Table 4................................8
Added Output Voltage Compliance Section................................17
Changes to Figure 31 ......................................................................23
Changes to Figure 32 ......................................................................24
Deleted Using the AD9834 Evaluation Board Section and the
Prototyping Area Section ...............................................................28
Added System Development Platform Section, AD9834 to
SPORT Interface Section, Figure 39, and Figure 40;
Renumbered Sequentially ..............................................................29
Changes to XO vs. External Clock Section and Power Supply
Section ..............................................................................................29
Deleted Bill of Materials, Table 19;
Renumbered Sequentially ..............................................................30
Added Evaluation Board Schematics Section and Figure 41 ....30
Added Figure 42 ..............................................................................31
Added Evaluation Board Layout Section and Figure 43 ............32
Added Figure 44 ..............................................................................33
Added Figure 45 ..............................................................................34
Changes to Ordering Guide...........................................................35
4/10—Rev. A to Rev. B
Changes to Comparator Section ...................................................15
Added Figure 28 ..............................................................................16
Changes to Serial Interface Section ..............................................17
8/06—Rev. 0 to Rev. A
Updated Format ................................................................. Universal
Changed to 75 MHz Complete DDS ............................... Universal
Changes to Features Section ............................................................1
Changes to Table 1 ............................................................................4
Changes to Table 2 ............................................................................6
Changes to Table 3 ............................................................................8
Added Figure 10, Figures Renumbered Sequentially ...................9
Added Figure 16 and Figure 17, Figures Renumbered
Sequentially......................................................................................10
Changes to Table 6 ..........................................................................19
Changes to Writing a Frequency Register Section .....................20
Changes to Figure 29 ......................................................................21
Changes to Table 19 ........................................................................30
Changes to Figure 38 ......................................................................28
2/03—Revision 0: Initial Version
Rev. C | Page 3 of 36
AD9834
SPECIFICATIONS
VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, T
A
= T
MIN
to T
MAX
, R
SET
= 6.8 kΩ, R
LOAD
= 200 Ω for IOUT and IOUTB, unless otherwise noted.
Table 1.
Parameter
2
SIGNAL DAC SPECIFICATIONS
Resolution
Update Rate
I
OUT
Full Scale
3
V
OUT
Max
V
OUT
Min
Output Compliance
4
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
DDS SPECIFICATIONS
Dynamic Specifications
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range (SFDR)
Wideband (0 to Nyquist)
Narrow Band (±200 kHz)
B Grade
C Grade
Clock Feedthrough
Wake-Up Time
COMPARATOR
Input Voltage Range
Input Capacitance
Input High-Pass Cutoff Frequency
Input DC Resistance
Input Leakage Current
OUTPUT BUFFER
Output Rise/Fall Time
Output Jitter
VOLTAGE REFERENCE
Internal Reference
REFOUT Output Impedance
5
Reference Temperature Coefficient
LOGIC INPUTS
Input High Voltage, V
INH
Min
Grade B, Grade C
1
Typ
Max
10
75
3.0
0.6
30
0.8
±1
±0.5
Unit
Bits
MSPS
mA
V
mV
V
LSB
LSB
Test Conditions/Comments
55
60
−66
−60
−78
−74
−50
1
−56
−56
−67
−65
dB
dBc
dBc
dBc
dBc
dBc
ms
V p-p
pF
MHz
MΩ
μA
ns
ps rms
f
MCLK
= 75 MHz, f
OUT
= f
MCLK
/4096
f
MCLK
= 75 MHz, f
OUT
= f
MCLK
/4096
f
MCLK
= 75 MHz, f
OUT
= f
MCLK
/75
f
MCLK
= 50 MHz, f
OUT
= f
MCLK
/50
f
MCLK
= 75 MHz, f
OUT
= f
MCLK
/75
1
10
4
5
10
12
120
1.12
1.18
1
100
1.24
AC-coupled internally
Using a 15 pF load
3 MHz sine wave, 0.6 V p-p
V
kΩ
ppm/°C
V
V
V
V
V
V
μA
pF
2.3 V to 2.7 V power supply
2.7 V to 3.6 V power supply
4.5 V to 5.5 V power supply
2.3 V to 2.7 V power supply
2.7 V to 3.6 V power supply
4.5 V to 5.5 V power supply
1.7
2.0
2.8
0.6
0.7
0.8
10
3
Input Low Voltage, V
INL
Input Current, I
INH
/I
INL
Input Capacitance, C
IN
Rev. C | Page 4 of 36
