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14-Bit CCD Signal Processor with V-Driver
and
Precision Timing
TM
Generator
AD9927
FEATURES
Integrated 18-channel V-driver
1.8 V AFETG core
Internal LDO regulator and charge pump circuitry
Compatibility with 3 V or 1.8 V systems
24 programmable vertical clock signals
Correlated double sampler (CDS) with −3 dB, 0 dB,
+3 dB, and +6 dB gain
6 dB to 42 dB, 10-bit variable gain amplifier (VGA)
14-bit, 40 MHz analog-to-digital converter (ADC)
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing
core with ~400 ps resolution
On-chip 3 V horizontal and RG drivers
General-purpose outputs (GPOs) for shutter and
system support
On-chip driver for external crystal
On-chip sync generator with external sync input
128-lead CSP_BGA package, 9 mm × 9 mm, 0.65 mm pitch
GENERAL DESCRIPTION
The AD9927 is a highly integrated CCD signal processor for
digital still camera applications. It includes a complete analog
front end with A/D conversion, combined with a full-function
programmable timing generator and 18-channel vertical driver
(V-driver). The timing generator is capable of supporting up to
24 vertical clock signals to control advanced CCDs. The on-
chip V-driver supports up to 18 channels for use with 5-field
CCDs. A
Precision Timing
core allows adjustment of high speed
clocks with approximately 400 ps resolution at 40 MHz
operation. The AD9927 also contains eight general-purpose
outputs, which can be used for shutter and system functions.
The analog front end includes black level clamping, CDS, VGA,
and a 14-bit ADC. The timing generator provides all the
necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate
pulses, substrate clock, and substrate bias control.
The AD9927 is specified over an operating temperature range
of –25°C to +85°C.
APPLICATIONS
Digital still cameras
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
AD9927
–3dB, 0dB, +3dB, +6dB
CCDIN
CDS
VGA
6dB TO 42dB
3V INPUT
1.8V OUTPUT
1.8V INPUT
3V OUTPUT
RG
HL
8
H1 TO H8
V1A-V6 (3-LEVEL)
V7-V15 (2-LEVEL)
SUBCK
XSUBCK
18
VERTICAL
DRIVER
XV1 TO XV24
24
VERTICAL
TIMING
CONTROL
8
05892-103
VREF
14-BIT
ADC
CLAMP
14
DOUT
LDO
REG
CHARGE
PUMP
INTERNAL CLOCKS
HORIZONTAL
DRIVERS
PRECISION
TIMING
GENERATOR
SL
INTERNAL
REGISTERS
SCK
SDATA
SYNC
GENERATOR
XSUBCNT
GP01 TO GP08
HD
VD SYNC CLI
CLO
RSTB
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD9927
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Specifications..................................................................................... 3
Digital Specifications ................................................................... 4
Analog Specifications................................................................... 5
Timing Specifications .................................................................. 6
Vertical Driver Specifications ..................................................... 7
Absolute Maximum Ratings............................................................ 8
Package Thermal Characteristics ............................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Terminology .................................................................................... 12
Typical Performance Characteristics ........................................... 13
Equivalent Circuits ......................................................................... 14
System Overview ............................................................................ 15
High Speed
Precision Timing
Core........................................... 16
Horizontal Clamping and Blanking......................................... 20
Horizontal Timing Sequence Example.................................... 26
Vertical Timing Generation ...................................................... 28
Vertical Sequences (VSEQ) ....................................................... 31
Internal Vertical Driver Connections...................................... 45
Vertical Timing Example........................................................... 53
Shutter Timing Control ............................................................. 55
Substrate Clock Operation (SUBCK) ...................................... 55
Field Counters............................................................................. 58
General-Purpose Outputs (GPO
S
) .......................................... 59
GP Look-Up Tables (LUT)........................................................ 63
Complete Exposure/Readout Operation
Using Primary Counter and GPO Signals .............................. 64
Manual Shutter Operation Using Enhanced SYNC Modes .... 66
Analog Front-End Description and Operation...................... 70
Power-Up Sequence for Master Mode..................................... 72
Standby Mode Operation .......................................................... 76
CLI Frequency Change.............................................................. 76
Circuit Layout Information........................................................... 78
Serial Interface Timing .............................................................. 82
Layout of Internal Registers ...................................................... 83
Updating New Register Values ................................................. 84
Complete Register Listing ............................................................. 85
Outline Dimensions ....................................................................... 99
Ordering Guide .......................................................................... 99
REVISION HISTORY
1/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 100
AD9927
SPECIFICATIONS
Table 1.
Parameter
TEMPERATURE RANGE
Operating
Storage
POWER SUPPLY VOLTAGE INPUTS
AVDD (AFE Analog Supply)
TCVDD (Timing Core Supply)
CLIVDD (CLI Input Supply)
RGVDD (RG, HL Driver)
HVDD (H1 to H8 Drivers)
DVDD (Digital Logic)
DRVDD (Parallel Data Output Drivers)
IOVDD (Digital I/O)
XVVDD (Vertical Output Drivers)
CP1P8 (CP Supply Input)
LDOIN (LDO Supply Input)
V-DRIVER POWER SUPPLY VOLTAGES
VDD1, VDD2 (V-Driver Logic)
VH1, VH2 (V-Driver High Supply)
VL1, VL2 (V-Driver Low Supply)
VM1, VM2 (V-Driver Mid Supply)
VLL (SUBCK Low Supply)
VMM (SUBCK Mid Supply)
POWER SUPPLY CURRENTS—40 MHz OPERATION
AVDD (1.8 V)
TCVDD (1.8 V)
CLIVDD (3 V)
RGVDD (3.3 V, 20 pF RG Load, 20 pF HL Load)
HVDD
1
(3.3 V, 480 pF Total Load on H1 to H8)
DVDD (1.8 V)
DRVDD (3 V, 10 pF Load on Each DOUT Pin)
IOVDD (3 V, Depends on Load and Output Frequency of Digital I/O)
XVVDD (3 V, Depends on Load and Output Frequency of XV Signals)
POWER SUPPLY CURRENTS—STANDBY MODE OPERATION
Standby1 Mode
Standby2 Mode
Standby3 Mode
MAXIMUM CLOCK RATE (CLI)
1
Min
−25
−65
1.6
1.6
1.6
2.7
2.7
1.6
1.6
2.7
2.7
1.6
2.25
2.7
11.5
−8.5
−1.5
−8.5
−4.0
Typ
Max
+85
+150
Unit
°C
°C
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
MHz
1.8
1.8
3.0
3.0
3.0
1.8
3.0
3.0
3.0
1.8
3.0
3.0
15.0
−7.5
0.0
−7.5
0.0
27
5
1.5
10
59
9.5
6
2
2
12
5
1.5
2.0
2.0
3.6
3.6
3.6
2.0
3.6
3.6
3.6
2.0
3.6
3.6
16.5
−5.5
+1.5
−5.5
+0.3
40
The total power dissipated by the HVDD (or RGVDD) supply can be approximated using the equation
Total HVDD Power
= [C
L
×
HVDD
×
Pixel Frequency]
×
HVDD
Reducing the capacitive load and/or reducing the HVDD supply reduces the power dissipation. C
L
is the total capacitance seen by all H-outputs.
Rev. 0 | Page 3 of 100
AD9927
DIGITAL SPECIFICATIONS
IOVDD = 1.6 V to 3.6 V, RGVDD = HVDD = 2.7 V to 3.6 V, C
L
= 20 pF, T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
LOGIC INPUTS (IOVDD)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS (IOVDD, XVDD, DRVDD)
High Level Output Voltage @ I
OH
= 2 mA
Low Level Output Voltage @ I
OL
= 2 mA
RG and H-DRIVER OUTPUTS (HVDD, RGVDD)
High Level Output Voltage @ Maximum Current
Low Level Output Voltage @ Maximum Current
Maximum Output Current (Programmable)
Maximum Load Capacitance (for Each Output)
Symbol
V
IH
V
IL
I
IH
I
IL
C
IN
V
OH
V
OL
V
OH
V
OL
Min
V
DD
− 0.6
0.6
10
10
10
V
DD
− 0.5
0.5
V
DD
− 0.5
0.5
18
60
Typ
Max
Unit
V
V
μA
μA
pF
V
V
V
V
mA
pF
Rev. 0 | Page 4 of 100
