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400 MSPS, 14-Bit, 1.8 V CMOS
Direct Digital Synthesizer
AD9953
FEATURES
400 MSPS internal clock speed
Integrated 14-bit DAC
32-bit tuning word
Phase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output)
Excellent dynamic performance
>80 dB SFDR @ 160 MHz (±100 kHz offset) A
OUT
Serial I/O control
1.8 V power supply
Software and hardware controlled power-down
48-lead TQFP/EP package
Support for 5 V input levels on most digital inputs
PLL REFCLK multiplier (4× to 20×)
Internal oscillator, can be driven by a single crystal
Phase modulation capability
Multichip synchronization
APPLICATIONS
Agile VHF/UHF LO frequency synthesis
FM chirp source for radar and scanning systems
Nonlinear-shaped PSK/FSK modulator
Test and measurement equipment
FUNCTIONAL BLOCK DIAGRAM
DDS CORE
RAM
DATA
32
M
U
X
PHASE
ACCUMULATOR
Z
–1
PHASE
OFFSET
19
COS(X)
14
DAC
AD9953
DAC_R
SET
IOUT
IOUT
1024
×
32
STATIC RAM
RAM ADDRESS
RAM CONTROL
FREQUENCY
TUNING WORD
RAM DATA
DDS CLOCK
PHASE
ACCUMULATOR
RESET
DDS CLOCK
Z
–1
14
SYSTEM
CLOCK
MUX
14
14
PHASE
OFFSET
WORD
SYNC_IN
32
10
I/O UPDATE
M
U
X
0
3
32
RAM DATA <31:18>
TIMING AND CONTROL LOGIC
OSK
PWRDWNCTL
SYNC_CLK
SYNC
÷4
CONTROL REGISTERS
OSCILLATOR/BUFFER
REFCLK
REFCLK
ENABLE
4×–20×
CLOCK
MULTIPLIER
M
U
X
SYSTEM
CLOCK
03357-0-001
CRYSTAL OUT
PS<1:0>
I/O PORT
RESET
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004–2009 Analog Devices, Inc. All rights reserved.
AD9953
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Electrical Specifications ................................................................... 4
Absolute Maximum Ratings............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration ............................................................................. 7
Pin Function Descriptions .............................................................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 12
Component Blocks ..................................................................... 12
Modes of Operation ................................................................... 19
Programming AD9953 Features .............................................. 22
Serial Port Operation ................................................................. 25
Instruction Byte .......................................................................... 27
Serial Interface Port Pin Description ....................................... 27
MSB/LSB Transfers .................................................................... 27
Suggested Application Circuits ..................................................... 29
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 30
REVISION HISTORY
5/09—Rev. 0 to Rev. A
Changes to Absolute Maximum Ratings Section ......................... 6
Changes to Table 3 ............................................................................ 8
Changes to Table 5 .......................................................................... 14
Changes to Figure 22 ...................................................................... 25
Changes to Serial Port Operation Section................................... 25
Changes to Serial Interface Port Pin Description Section ........ 27
Changes to Figure 29 ...................................................................... 29
Updated Outline Dimensions ....................................................... 30
Changes to Ordering Guide .......................................................... 30
1/04—Revision 0: Initial Version
Rev. A | Page 2 of 32
AD9953
GENERAL DESCRIPTION
The AD9953 is a direct digital synthesizer (DDS) featuring a
14-bit DAC operating up to 400 MSPS. The AD9953 uses
advanced DDS technology, coupled with an internal high speed,
high performance DAC to form a digitally programmable,
complete high frequency synthesizer capable of generating a
frequency-agile analog output sinusoidal waveform at up to
200 MHz. The AD9953 includes an integrated 1024 × 32 static
RAM to support flexible frequency sweep capability in several
modes. The AD9953 is designed to provide fast frequency
hopping and fine tuning resolution (32-bit frequency tuning
word). The frequency tuning and control words are loaded into
the AD9953 via a serial I/O port.
The AD9953 is specified to operate over the extended industrial
temperature range of –40°C to +105°C.
Rev. A | Page 3 of 32
AD9953
ELECTRICAL SPECIFICATIONS
Table 1. Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, R
SET
= 3.92 kΩ, External Reference Clock
Frequency = 20 MHz with REFCLK Multiplier Enabled at 20×. DAC Output Must Be Referenced to AVDD, Not AGND.
Parameter
REF CLOCK INPUT CHARACTERISTICS
Frequency Range
REFCLK Multiplier Disabled
REFCLK Multiplier Enabled at 4×
REFCLK Multiplier Enabled at 20×
Input Capacitance
Input Impedance
Duty Cycle
Duty Cycle with REFCLK Multiplier Enabled
REFCLK Input Power
1
DAC OUTPUT CHARACTERISTICS
Resolution
Full-Scale Output Current
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Capacitance
Residual Phase Noise @ 1 kHz Offset, 40 MHz A
OUT
REFCLK Multiplier Enabled @ 20×
REFCLK Multiplier Enabled @ 4×
REFCLK Multiplier Disabled
Voltage Compliance Range
Wideband SFDR
1 MHz to 10 MHz Analog Out
10 MHz to 40 MHz Analog Out
40 MHz to 80 MHz Analog Out
80 MHz to 120 MHz Analog Out
120 MHz to 160 MHz Analog Out
Narrow-Band SFDR
40 MHz Analog Out (±1 MHz)
40 MHz Analog Out (±250 kHz)
40 MHz Analog Out (±50 kHz)
40 MHz Analog Out (±10 kHz)
80 MHz Analog Out (±1 MHz)
80 MHz Analog Out (±250 kHz)
80 MHz Analog Out (±50 kHz)
80 MHz Analog Out (±10 kHz)
120 MHz Analog Out (±1 MHz)
120 MHz Analog Out (±250 kHz)
120 MHz Analog Out (±50 kHz)
120 MHz Analog Out (±10 kHz)
160 MHz Analog Out (±1 MHz)
160 MHz Analog Out (±250 kHz)
160 MHz Analog Out (±50 kHz)
160 MHz Analog Out (±10 kHz)
Temp
Min
Typ
Max
Unit
FULL
FULL
FULL
25°C
25°C
25°C
25°C
FULL
1
20
4
3
1.5
50
35
–15
0
14
10
400
100
20
65
+3
MHz
MHz
MHz
pF
kΩ
%
%
dBm
Bits
mA
%FS
μA
LSB
LSB
pF
dBc/Hz
dBc/Hz
dBc/Hz
V
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
5
–10
15
+10
0.6
1
2
5
–105
–115
–132
AVDD – 0.5
73
67
62
58
52
87
89
91
93
85
87
89
91
83
85
87
89
81
83
85
87
AVDD + 0.5
Rev. A | Page 4 of 32
嵌入式系统
