ADC10731/ADC10732/ADC10734/ADC10738 10-Bit Plus Sign Serial I/O A/D Converters with Mux,
Sample/Hold and Reference
May 1999
ADC10731/ADC10732/ADC10734/ADC10738
10-Bit Plus Sign Serial I/O A/D Converters with Mux,
Sample/Hold and Reference
General Description
This series of CMOS 10-bit plus sign successive approxima-
tion A/D converters features versatile analog input multiplex-
ers, sample/hold and a 2.5V band-gap reference. The 1-, 2-,
4-, or 8-channel multiplexers can be software configured for
single-ended or differential mode of operation.
An input sample/hold is implemented by a capacitive refer-
ence ladder and sampled-data comparator. This allows the
analog input to vary during the A/D conversion cycle.
In the differential mode, valid outputs are obtained even
when the negative inputs are greater than the positive be-
cause of the 10-bit plus sign output data format.
The serial I/O is configured to comply with the NSC MI-
CROWIRE
™
serial data exchange standard for easy inter-
face to the COPS
™
and HPC
™
families of controllers, and
can easily interface with standard shift registers and micro-
processors.
n
n
n
n
n
n
n
Software or hardware power down
Analog input sample/hold function
Ratiometric or absolute voltage referencing
No zero or full scale adjustment required
No missing codes over temperature
TTL/CMOS input/output compatible
Standard DIP and SO packages
Key Specifications
n
n
n
n
n
n
n
Resolution
Single supply
Power dissipation
In powerdown mode
Conversion time
Sampling rate
Band-gap reference
10 bits plus sign
5V
37 mW (Max)
18 µW
5µs (Max)
74 kHz (Max)
2.5V
±
2% (Max)
Features
n
0V to 5V analog input range with single 5V power
supply
n
Serial I/O (MICROWIRE compatible)
n
1-, 2-, 4-, or 8-channel differential or single-ended
multiplexer
Applications
n
Medical instruments
n
Portable and remote instrumentation
n
Test equipment
ADC10738 Simplified Block Diagram
DS011390-1
COPS
™
, HPC
™
and MICROWIRE
™
are trademarks of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS011390
www.national.com
Connection Diagrams
DS011390-2
Top View
See NS Package Number M16B
DS011390-4
Top View
See NS Package Number M20B
DS011390-3
Top View
See NS Package Number M20B
DS011390-5
Top View
See NS Package Number M24B
SSOP Package
DS011390-34
See NS Package Number MSA20
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2
Ordering Information
Industrial Temperature Range
−40˚C
≤
T
A
≤
+85˚C
ADC10731CIWM
ADC10732CIWM
ADC10734CIMSA
ADC10734CIWM
ADC10738CIWM
M16B
M20B
MSA20
M20B
M24B
Package
Pin Descriptions
CLK
The clock applied to this input controls the suc-
cessive approximation conversion time interval,
the acquisition time and the rate at which the se-
rial data exchange occurs. The rising edge loads
the information on the DI pin into the multiplexer
address shift register. This address controls
which channel of the analog input multiplexer
(MUX) is selected. The falling edge shifts the
data resulting from the A/D conversion out on
DO. CS enables or disables the above functions.
The clock frequency applied to this input can be
between 5 kHz and 3 MHz.
This is the serial data input pin. The data applied
to this pln is shifted by CLK into the multiplexer
address register.
Tables 1, 2, 3
show the multi-
plexer address assignment.
The data output pin. The A/D conversion result
(DB0-SIGN) are clocked out by the failing edge
of CLK on this pin.
V
REF
−
The negative voltage reference input. In order to
maintain accuracy, the voltage at this pin must
not go below GND − 50 mV or exceed AV
+
+ 50 mV.
These are the analog and digital power supply
pins. These pins should be tied to the same
power supply and bypassed separately. The op-
erating voltage range of AV
+
and DV
+
is 4.5 V
DC
to 5.5 V
DC
.
This is the digital ground pin.
This is the analog ground pin.
AV
+
, DV
+
DGND
AGND
DI
DO
This is the chip select input pin. When a logic low
is applied to this pin, the rising edge of CLK
shifts the data on DI into the address register.
This low also brings DO out of TRI-STATE after
a conversion has been completed.
PD
This is the power down input pin. When a logic
high is applied to this pin the A/D is powered
down. When a low is applied the A/D is powered
up.
SARS
This is the successive approximation register
status output pin. When CS is high this pin is in
TRI-STATE. With CS low this pin is active high
when a conversion is in progress and active low
at all other times.
CH0–CH7 These are the analog inputs of the MUX. A chan-
nel input is selected by the address information
at the DI pin, which is loaded on the rising edge
of CLK into the address register (see
Tables 1, 2,
3).
The voltage applied to these inputs should not
exceed AV
+
or go below GND by more than
50 mV. Exceeding this range on an unselected
channel will corrupt the reading of a selected
channel.
COM
This pin is another analog input pln. It can be
used as a “pseudo ground” when the analog
multiplexer is single-ended.
V
REF
+
This is the positive analog voltage reference in-
put. In order to malntaln accuracy, the voltage
range V
REF
(V
REF
= V
REF
+–V
REF
−) is 0.5 V
DC
to
5.0 V
DC
and the voltage at V
REF
+ cannot exceed
AV
+
+50 mV.
CS
3
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Absolute Maximum Ratings
(Notes 1, 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
+
= AV
+
= DV
+
)
Total Reference Voltage
(V
REF
+–V
REF
−)
Voltage at Inputs and Outputs
Input Current at Any Pin (Note 4)
Package Input Current (Note 4)
Package Dissipation at T
A
= 25˚C
(Note 5)
ESD Susceptability (Note 6)
Human Body Model
Machine Model
Soldering Information
N packages (10 seconds)
SO Package (Note 7)
6.5V
6.5V
V
+
+ 0.3V to −0.3V
30 mA
120 mA
500 mW
2500V
150V
260˚C
Vapor Phase (60 seconds)
Infrared (15 seconds)
Storage Temperature
215˚C
220˚C
−40˚C to +150˚C
Operating Ratings
(Notes 2, 3)
Operating Temperature Range
ADC10731CIWM,
ADC10732CIWM,
ADC10734CIWM,
ADC10734CIMSA,
ADC10738CIWM
Supply Voltage
(V
+
= AV
+
= DV
+
)
V
REF
+
V
REF
−
V
REF
(V
REF
+–V
REF
−)
T
MIN
≤
T
A
≤
T
MAX
−40˚C
≤
T
A
≤
+85˚C
+4.5V to +5.5V
AV +50 mV to −50 mV
AV
+
+50 mV to −50 mV
+0.5V to V
+
+
Electrical Characteristics
The following specifications apply for V
+
= AV
+
= DV
+
= +5.0 V
DC
, V
REF
+ = 2.5 V
DC
, V
REF
− = GND, V
IN
− = 2.5V for Signed
Characteristics, V
IN
− = GND for Unsigned Characteristics and f
CLK
= 2.5 MHz unless otherwise specified.
Boldface limits ap-
ply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= +25˚C. (Notes 8, 9, 10)
Symbol
Parameter
Conditions
Typical
(Note 11)
SIGNED STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
TUE
INL
Total Unadjusted Error (Note 13)
Positive and Negative Integral
Linearity Error
Positive and Negative
Full-Scale Error
Offset Error
Power Supply Sensitivity
Offset Error
+ Full-Scale Error
− Full-Scale Error
DC Common Mode Error (Note 14)
Multiplexer Channel to
Channel Matching
UNSIGNED STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
TUE
INL
Total Unadjusted Error (Note 13)
Integral Linearity Error
Full-Scale Error
Offset Error
Power Supply Sensitivity
Offset Error
Full-Scale Error
DC Common Mode Error (Note 14)
Multiplexer Channel to Channel
Matching
V
+
= +5.0V
±
10%
V
REF
+ = 4.096V
V
IN
+ = V
IN
− = V
IN
where
+5.0V
≥
V
IN
≥
0V
V
REF
+ = 4.096V
V
REF
+ = 4.096V
V
REF
+ = 4.096V
V
REF
+ = 4.096V
V
REF
+ = 4.096V
10
Bits
LSB
LSB
V
IN
+ = V
IN
− = V
IN
where
5.0V
≥
V
IN
≥
0V
V
+
= +5.0V
±
10%
10 + Sign
Bits
LSB(max)
LSB(max)
LSB(max)
LSB(max)
LSB(max)
LSB(max)
LSB(max)
LSB(max)
LSB
Limits
(Note 12)
Units
(Limits)
±
2.0
±
1.25
±
1.5
±
1.5
±
0.2
±
0.2
±
0.1
±
0.1
±
0.1
±
1.0
±
1.0
±
0.75
±
0.33
±
0.75
±
0.50
±
1.25
±
1.25
±
0.1
±
0.1
±
0.1
±
0.1
LSB(max)
LSB(max)
LSB
LSB
LSB
LSB
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4
Electrical Characteristics
(Continued)
The following specifications apply for V
+
= AV
+
= DV
+
= +5.0 V
DC
, V
REF
+ = 2.5 V
DC
, V
REF
− = GND, V
IN
− = 2.5V for Signed
Characteristics, V
IN
− = GND for Unsigned Characteristics and f
CLK
= 2.5 MHz unless otherwise specified.
Boldface limits ap-
ply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= +25˚C. (Notes 8, 9, 10)
Symbol
Parameter
Conditions
Typical
(Note 11)
DYNAMIC SIGNED CONVERTER CHARACTERISTICS
S/(N+D)
ENOB
THD
IMD
Signal-to-Noise Plus Distortion Ratio
Effective Number of Bits
Total Harmonic Distortion
Intermodulation Distortion
Full-Power Bandwidth
V
IN
= 4.85 V
PP
,
and f
IN
= 1 kHz to 15 kHz
V
IN
= 4.85 V
PP
,
and f
IN
= 1 kHz to 15 kHz
V
IN
= 4.85 V
PP
,
and f
IN
= 1 kHz to 15 kHz
V
IN
= 4.85 V
PP
,
and f
IN
= 1 kHz to 15 kHz
V
IN
= 4.85 V
PP
, where
S/(N + D) Decreases
3 dB
f
IN
= 15 kHz
67
10.8
−78
−85
380
dB
Bits
dB
dB
kHz
Limits
(Note 12)
Units
(Limits)
Multiplexer Channel to Channel
Crosstalk
S/(N+D)
Signal-to-Noise Plus Distortion Ratio
−80
dB
DYNAMIC UNSIGNED CONVERTER CHARACTERISTIC
V
REF
+ = 4.096V,
V
IN
= 4.0 V
PP
, and
f
IN
= 1 kHz to 15 kHz
V
REF
+ = 4.096V,
V
IN
= 4.0 V
PP
, and
f
IN
= 1 kHz to 15 kHz
THD
Total Harmonic Distortion
V
REF
+ = 4.096V,
V
IN
= 4.0 V
PP
, and
f
IN
= 1 kHz to 15 kHz
V
REF
+ = 4.096V,
V
IN
= 4.0 V
PP
, and
f
IN
= 1 kHz to 15 kHz
Full-Power Bandwidth
V
IN
= 4.0 V
PP
,
V
REF
+ = 4.096V,
where S/(N+D) decreases
3 dB
f
IN
= 15 kHz,
V
REF
+ = 4.096V
−73
dB
9.8
Bits
60
dB
Effective Bits
−70
dB
IMD
Intermodulation Distortion
380
kHz
Multiplexer Channel to Channel
Crosstalk
Reference Input Resistance
−80
dB
REFERENCE INPUT AND MULTIPLEXER CHARACTERISTICS
7
5.0
9.5
C
REF
Reference Input Capacitance
MUX Input Voltage
C
IM
MUX Input Capacitance
Off Channel Leakage Current
(Note 15)
On Channel Leakage Current
On Channel = 5V and
Off Channel = 0V
On Channel = 0V and
Off Channel = 5V
On Channel = 5V and
47
−0.4
0.4
0.4
−3.0
3.0
3.0
70
−50
AV
+
+50 mV
kΩ
kΩ(min)
kΩ(max)
pF
mV(min)
(max)
pF
µA(max)
µA(max)
µA(max)
5
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