Changes to Ordering Guide .......................................................... 17
9/08—Rev. 0 to Rev. A
Changes to Figure 22 ...................................................................... 13
1/07—Revision 0: Initial Version
Rev. B | Page 2 of 20
Data Sheet
SPECIFICATIONS
ADF4113HV
AV
DD
= DV
DD
= 3 V ± 10%, 5 V ± 10%; 13.5 V < V
P
≤ 16.5 V; AGND = DGND = CPGND = 0 V; R
SET
= 4.7 kΩ; dBm referred to 50 Ω;
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Operating temperature range for B version: −40°C to +85°C.
Table 1.
Parameter
RF CHARACTERISTICS (3 V)
RF Input Sensitivity
RF Input Frequency
Prescaler Output Frequency
2
RF CHARACTERISTICS (5 V)
RF Input Sensitivity
RF Input Frequency
Prescaler Output Frequency
REF
IN
CHARACTERISTICS
REF
IN
Input Frequency
Reference Input Sensitivity
REF
IN
Input Capacitance
REF
IN
Input Current
PHASE DETECTOR FREQUENCY
CHARGE PUMP
I
CP
Sink/Source
High Value
Low Value
Absolute Accuracy
R
SET
Range
I
CP
Three-State Leakage Current
Sink and Source Current Matching
I
CP
vs. V
CP
I
CP
vs. Temperature
LOGIC INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
/I
INL
, Input Current
C
IN
, Input Capacitance
LOGIC OUTPUTS
V
OH
, Output High Voltage
V
OL
, Output Low Voltage
POWER SUPPLIES
AV
DD
DV
DD
V
P
I
DD 5
(AI
DD
+ DI
DD
)
I
P
Low Power Sleep Mode
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
6
1
2
B Version
−15/0
0.2/3.7
165
−10/0
0.2/3.7
0.2/4.0
200
5/150
0.4/AV
DD
1.0/AV
DD
10
±100
5
B Chips
1
−15/0
0.2/3.7
165
−10/0
0.2/3.7
0.2/4.0
200
5/150
0.4/AV
DD
1.0/AV
DD
10
±100
5
Unit
dBm min/max
GHz min/max
MHz max
dBm min/max
GHz min/max
GHz min/max
MHz max
MHz min/max
V p-p min/max
V p-p min/max
pF max
µA max
MHz max
Test Conditions/Comments
For lower frequencies, ensure SR > 130 V/μs
For lower frequencies, ensure SR > 130 V/µs
Input level = −5 dBm
For f < 5 MHz, ensure SR > 100 V/µs
AV
DD
= 3.3 V, biased at AV
DD
/2
3
For f ≥ 10 MHz, AV
DD
= 5 V, biased at AV
DD
/2
3, 4
R
SET
= 4.7 kΩ
640
80
2.5
3.9/10
5
3
1.5
2
0.8 × DV
DD
0.2 × DV
DD
±1
10
DV
DD
− 0.4
0.4
2.7/5.5
AV
DD
13.5/16.5
16
0.25
1
−212
640
80
2.5
3.9/10
5
3
1.5
2
0.8 × DV
DD
0.2 × DV
DD
±1
10
DV
DD
− 0.4
0.4
2.7/5.5
AV
DD
13.5/16.5
11
0.25
1
−212
μA typ
µA typ
% typ
kΩ typ
nA max
% typ
% typ
% typ
V min
V max
µA max
pF max
V min
V max
V min/V max
V min/V max
mA max
mA max
µA typ
dBc/Hz typ
I
OH
= 500 µA
I
OL
= 500 µA
1 V ≤ V
CP
≤ V
P
– 1 V
1 V ≤ V
CP
≤ V
P
– 1 V
V
CP
= V
P
/2
11 mA typical
T
A
= 25°C
The B chip specifications are given as typical values.
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
3
AC coupling ensures AV
DD
/2 bias.
4
Guaranteed by characterization.
5
T
A
= 25
o
C; AV
DD
= DV
DD
= 5.5 V; P = 16; RF
IN
= 900 MHz.
6
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PN
TOT
, and subtracting 20logN (where N is the N divider
value) and 10logf
PFD
: PN
SYNTH
= PN
TOT
− 10logf
PFD
− 20logN.
Rev. B | Page 3 of 20
ADF4113HV
TIMING CHARACTERISTICS
Guaranteed by design but not production tested. AV
