a
FEATURES
Total I
DD
: 7.1 mA
Bandwidth/RF 3.0 GHz
ADF4217L/ADF4218L, IF 1.1 GHz
ADF4219L, IF 1.0 GHz
2.6 V to 3.3 V Power Supply
1.8 V Logic Compatibility
Separate V
P
Allows Extended Tuning Voltage
Selectable Dual Modulus Prescaler
Selectable Charge Pump Currents
Charge Pump Current Matching of 1%
3-Wire Serial Interface
Power-Down Mode
APPLICATIONS
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base Stations for Wireless Radio (GSM, PCS, DCS, WCDMA)
Wireless LANs
Communications Test Equipment
Cable TV Tuners (CATV)
Dual Low Power
Frequency Synthesizers
ADF4217L/ADF4218L/ADF4219L
GENERAL DESCRIPTION
The ADF4217L/ADF4218L/ADF4219L are low power dual
frequency synthesizers that can be used to implement local
oscillators in the up-conversion and down-conversion sections
of wireless receivers and transmitters. They can provide the LO
for both the RF and IF sections. They consist of a low noise
digital PFD (phase frequency detector), a precision charge pump, a
programmable reference divider, programmable A and B counters,
and a dual modulus prescaler (P/P + 1). The A and B counters,
in conjunction with the dual modulus prescaler (P/P + 1),
implement an N divider (N = BP + A). In addition, the 14-bit
reference counter (R Counter) allows selectable REFIN fre-
quencies at the PFD input. A complete PLL (phase-locked
loop) can be implemented if the synthesizers are used with an
external loop filter and VCOs (voltage controlled oscillators).
Control of all the on-chip registers is via a simple 3-wire interface
with 1.8 V compatibility. The devices operate with a power supply
ranging from 2.6 V to 3.3 V and can be powered down when
not in use.
FUNCTIONAL BLOCK DIAGRAM
ADF4219L ONLY
NC
V
DD
1
V
DD
2
V
P
1
V
P
2
N = BP + A
11(13)-BIT IF
B COUNTER
IF
IN
A
IF
IN
B
ADF4217L
ADF4218L
ONLY
REF
IN
IF
PRESCALER
6(5)-BIT IF
A COUNTER
IF
LOCK
DETECT
14(15)-BIT IF
R COUNTER
CLOCK
DATA
LE
22-BIT
DATA
SDOUT
REGISTER
14(15)-BIT RF
R COUNTER
RF
LOCK
DETECT
PHASE
COMPARATOR
ADF4217L/
ADF4218L/
ADF4219L
CHARGE
PUMP
CP
IF
BUFFER
OUTPUT
MUX
MUXOUT
N = BP + A
11(13)-BIT RF
B COUNTER
RF
IN
A
RF
IN
B
RF
PRESCALER
6(5)-BIT RF
A COUNTER
PHASE
COMPARATOR
CHARGE
PUMP
CP
RF
FEATURES IN ( ) REFER TO ADF4219L
NC = NO CONNECT
DGND
RF
AGND
RF
DGND
IF
AGND
IF
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
ADF4217L/ADF4218L/ADF4219L–SPECIFICATIONS
1
(V
DD
1 = V
DD
2 = 2.6 V to 3.3 V; V
P
1, V
P
2 = V
DD
to 5.5 V; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
BChips
2
(Typical)
Parameter
RF CHARACTERISTICS
RF Input Frequency (RF
IN
)
ADF4217L, ADF4218L
ADF4217L, ADF4218L
ADF4219L
RF Input Sensitivity
ADF4217L, ADF4218L
ADF4219L
IF Input Frequency (IF
IN
)
ADF4217L/ADF4218L
ADF4219L P = 16/17
ADF4219L P = 8/9
IF Input Sensitivity
Maximum Allowable Prescaler
Output Frequency
3
REFIN CHARACTERISTICS
Reference Input Frequency
Reference Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency
4
CHARGE PUMP
I
CP
Sink/Source
High Value
Low Value
Absolute Accuracy
I
CP
Three-State Leakage Current
Sink and Source Current Matching
I
CP
vs. V
CP
I
CP
vs. Temperature
LOGIC INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
/I
INL
, Input Current
C
IN
, Input Capacitance
Reference Input Current
LOGIC OUTPUTS
V
OH
, Output High Voltage
V
OL
, Output Low Voltage
POWER SUPPLIES
V
DD
1
V
DD
2
V
P
1, V
P
2
I
DD
(RF + IF)
5
(RF only)
5
(IF only)
5
I
P
(I
P
1 + I
P
2)
Low Power Sleep Mode
B Version
1
Unit
Test Conditions/Comments
Use a square wave for operation
below minimum frequency spec.
0.15/3.0
0.15/2.5
0.8/2.2
–15/0
–20/0
0.045/1.1
0.045/1.0
0.045/0.55
–15/0
188
10/110
0.5
10
±
100
56
0.15/3.0
0.15/2.5
0.8/2.2
–15/0
–20/0
0.045/1.1
0.045/1.0
0.045/0.55
–15/0
188
10/110
0.5
10
±
100
56
GHz min/max
GHz min/max
GHz min/max
dBm min/max
dBm min/max
GHz min/max
GHz min/max
GHz min/max
dBm min/max
MHz max
MHz min/max
V p-p min
pF max
µA
max
MHz max
For f < 10 MHz, use dc-coupled
square wave, (0 to V
DD
).
AC-coupled. When dc-coupled,
0 to V
DD
max.
(CMOS compatible)
–15 dBm minimum input signal
–10 dBm minimum input signal
–10 dBm minimum input signal
–10 dBm minimum input signal
–15 dBm minimum input signal
–20 dBm minimum input signal
4
1
1
1
6
5
2
1.4
0.6
±
1
10
±
100
V
DD
– 0.4
0.4
2.6/3.3
V
DD
1
V
DD
1/5.5 V
10
7
5
0.6
1
4
1
1
1
6
5
2
1.4
0.6
±
1
10
±
100
V
DD
– 0.4
0.4
2.6/3.3
V
DD
1
V
DD
1/5.5 V
10
7
5
0.6
1
mA typ
mA typ
% typ
nA typ
% max
% max
% typ
V min
V max
µA
max
pF max
µA
max
V min
V max
V min/V max
V min/V max
mA max
mA
mA
mA typ
µA
typ
0.5 V < V
CP
< V
P
– 0.5, 1% typ
0.5 V < V
CP
< V
P
– 0.5, 0.1% typ
V
CP
= V
P
/2
I
OH
= 1 mA
I
OL
= 1 mA
7.1 mA typ
4.7 mA typ
3.4 mA typ
T
A
= 25°C
–2–
REV. C
ADF4217L/ADF4218L/ADF4219L
Parameter
NOISE CHARACTERISTICS
6
RF Phase Noise Floor
7
IF Phase Noise Floor
7
Phase Noise Performance
8
RF
9
RF
10
IF
11
IF
12
Spurious Signals
RF
9
RF
10
IF
11
IF
12
B Version
1
–171
–163
–167
–159
–75
–90
–77
–86
–78/–85
–80/–84
–79/–86
–80/–84
BChips
2
(Typical)
–171
–163
–167
–159
–75
–90
–77
–86
–78/–85
–80/–84
–79/–86
–80/–84
Unit
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc typ
dBc typ
dBc typ
dBc typ
Test Conditions/Comments
@ 30 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ 30 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ VCO Output
1.95 GHz Output; 30 kHz PFD
900 MHz Output; 200 kHz PFD
900 MHz Output; 30 kHz PFD
900 MHz Output; 200 kHz PFD
Measured at Offset of f
PFD
/2f
PFD
NOTES
1
Operating temperature range is as follows: B Version: –40°C to +85°C.
2
The BChip specifications are given as typical values.
3
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency
that is less than this value.
4
Guaranteed by design. Sample tested to ensure compliance.
5
This includes relevant I
P
.
6
V
DD
= 3 V; P = 16/32; IF
IN
/RF
IN
for ADF4218L, ADF4219L = 540 MHz/900 MHz.
7
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).
8
The phase noise is measured with the EVAL-ADF421xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN
for the synthesizer. (f
REFOUT
= 10 MHz @ 0 dBm.)
9
f
REFIN
= 10 MHz; f
PFD
= 30 kHz; Offset frequency = 1 kHz; f
RF
= 1.95 GHz; N = 65000; Loop B/W = 3 kHz
10
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
RF
= 900 MHz; N = 4500; Loop B/W = 20 kHz
11
f
REFIN
= 10 MHz; f
PFD
= 30 kHz; Offset frequency = 1 kHz; f
IF
= 900 MHz; N = 30000; Loop B/W = 3 kHz
12
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
IF
= 900 MHz; N = 4500; Loop B/W = 20 kHz
Specifications subject to change without notice.
TIMING CHARACTERISTICS
Limit at
T
MIN
to T
MAX
(B Version)
10
10
25
25
10
50
(V
DD
1 = V
DD
2 = 3 V 10%, 5 V 10%; V
DD
1, V
DD
2
≤
V
P
1,
V
P
2
≤
6.0 V ; AGND
RF1
= DGND
RF1
= AGND
RF2
= DGND
RF2
= 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulsewidth
Guaranteed by design but not production tested.
t
3
CLOCK
t
4
t
1
DATA
DB21 (MSB)
DB20
t
2
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
6
LE
t
5
LE
Figure 1. Timing Diagram
REV. C
–3–
ADF4217L/ADF4218L/ADF4219L
ABSOLUTE MAXIMUM RATINGS
1, 2
(
T
A
= 25°C, unless otherwise noted.)
V
DD
1 to GND
3
. . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.6 V
V
DD
1 to V
DD
2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
V
P
1, V
P
2 to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.8 V
V
P
1, V
P
2 to V
DD
1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V
P
+ 0.3 V
REF
IN
, RF1
IN
(A, B), IF
IN
(A, B)
to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
RF
IN
A to RF
IN
B . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
320 mV
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
TSSOP
JA
Thermal Impedance . . . . . . . . . . . . . 150.4°C/W
LGA
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112°C/W
Lead Temperature, Soldering
TSSOP, Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . 215°C
TSSOP, Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . 220°C
LGA, Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . 240°C
LGA, Infrared (20 sec) . . . . . . . . . . . . . . . . . . . . . . . 240°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
2
This device is a high performance RF integrated circuit with an ESD rating of
< 2 kV and is ESD sensitive. Proper precautions should be taken for handling and
assembly.
3
GND = AGND = DGND = 0 V.
ORDERING GUIDE
Model
ADF4217L/ADF4218L/ADF4219LBRU
ADF4217L/ADF4218L/ADF4219LBCC
*Contact
the factory for chip availability.
Temperature
Range
–40°C to +85°C
–40°C to +85°C
Package
Description
Thin Shrink Small Outline Package (TSSOP)
Chip Array CASON (LGA)
Package
Option
*
RU-20
CC-24
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although the ADF4217L/
ADF4218L/ADF4219L feature proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
REV. C
ADF4217L/ADF4218L/ADF4219L
PIN CONFIGURATIONS
TSSOP
V
DD
1
V
P
1
CP
RF
DGND
RF
RF
IN
A
RF
IN
B
AGND
RF
REF
IN
DGND
IF
MUXOUT
1
2
3
4
5
6
7
8
9
10
20
19
18
17
TSSOP
V
DD
2
V
P
2
CP
IF
DGND
IF
IF
INA
IF
INB
AGND
IF
LE
DATA
CLK
V
DD
1
V
P
1
CP
RF
DGND
RF
RF
IN
A
RF
IN
B
AGND
RF
REF
IN
DGND
IF
MUXOUT
1
2
3
4
5
6
7
8
9
10
20
19
18
17
V
DD
2
V
P
2
CP
IF
DGND
IF
IF
IN
AGND
IF
NC
LE
DATA
CLK
ADF4217L/
ADF4218L
16
15
14
13
12
11
ADF4219L
16
15
14
13
12
11
CHIP SCALE
CHIP SCALE
V
DD
1
V
DD
2
23
V
DD
1
V
DD
2
V
P
2
24
24
23
22
21
20
19
NC
V
P
1
CP
RF
DGND
RF
RF
IN
A
RF
IN
B
AGND
RF
REF
IN
NC
1
2
3
4
5
6
7
8
9
10
11
12
NC
CP
IF
DGND
IF
IF
IN
A
IF
IN
B
AGND
IF
LE
DATA
NC
NC
V
P
1
CP
RF
DGND
RF
RF
IN
A
RF
IN
B
AGND
RF
REF
IN
NC
V
P
2
22
21
20
19
18
1
2
3
4
5
6
7
8
9
10
11
12
NC
CP
IF
DGND
IF
IF
IN
AGND
IF
NC
LE
DATA
NC
ADF4217L/
ADF4218L
18
17
16
15
14
13
ADF4219L
17
16
15
14
13
MUXOUT
DGND
IF
MUXOUT
DGND
IF
CLK
NC = NO INTERNAL CONNECT
NC = NO INTERNAL CONNECT
REV. C
–5–
CLK
