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Full-Duplex, Low Power,
Slew Rate Limited, EIA RS-485 Transceivers
ADM488A/ADM489A
FEATURES
Complies with ANSI TIA/EIA-485-A-1998 and
ISO 8482: 1987(E)
250 kbps data rate
Single 5 V ± 10% supply
−7 V to +12 V bus common-mode range
Connect up to 32 nodes on the bus
Reduced slew rate for low EM interference
Short-circuit protection
30 µA supply current
FUNCTIONAL BLOCK DIAGRAMS
ADM488A
A
RO
R
B
Z
DI
D
08498-001
08498-002
Y
Figure 1. ADM488A
ADM489A
A
RO
RE
DE
Z
DI
D
Y
R
B
APPLICATIONS
Low power RS-485 and RS-422 systems
DTE-DCE interface
Packet switching
Local area networks
Data concentration
Data multiplexers
Integrated services digital network (ISDN)
GENERAL DESCRIPTION
The ADM488A and ADM489A are low power, differential line
transceivers suitable for communication on multipoint bus
transmission lines. They are intended for balanced data
transmission and comply with both RS-485 and RS-422
standards of the Electronics Industries Association (EIA). Both
products contain a single differential line driver and a single
differential line receiver, making them suitable for full-duplex
data transfer. The ADM489A contains an additional receiver
and driver enable control.
The input impedance is 12 kΩ, allowing 32 transceivers to be
connected on the bus. The ADM488A/ADM489A operate from
a single 5 V ± 10% power supply.
Figure 2. ADM489A
Excessive power dissipation that is caused by bus contention or
output shorting is prevented by a thermal shutdown circuit. This
feature forces the driver output into a high impedance state if,
during fault conditions, a significant temperature increase is
detected in the internal driver circuitry.
The receiver contains a fail-safe feature that results in a logic
high output state if the inputs are unconnected (floating).
The ADM488A/ADM489A are fabricated on BiCMOS, an
advanced mixed technology process combining low power
CMOS with fast switching bipolar technology.
The ADM488A/ADM489A are fully specified over the industrial
temperature range and are available in SOIC and MSOP packages.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781.329.4700
Fax: 781.461.3113 ©2009-2010 Analog Devices, Inc. All rights reserved.
ADM488A/ADM489A
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ..............................................8
Test Circuits........................................................................................9
Switching Characteristics .......................................................... 10
Theory of Operation ...................................................................... 11
Applications Information .............................................................. 13
Differential Data Transmission ................................................ 13
Cable and Data Rate................................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 15
REVISION HISTORY
11/10—Rev. 0 to Rev. A
Changes to Table 2 ............................................................................ 4
Changes to Figure 20 ...................................................................... 11
Changes to Figure 21 ...................................................................... 12
Added New Figure 23, Renumbered Subsequent Figures,
Moved Old Figure 23 to New Figure 25 ...................................... 14
Changes to Ordering Guide .......................................................... 15
10/09—Revision 0: Initial Version
Rev. A | Page 2 of 16
ADM488A/ADM489A
SPECIFICATIONS
V
CC
= 5 V ± 10%; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
DRIVER
Differential Output Voltage
Symbol
V
OD
2.0
1.5
1.5
Δ|V
OD
| for Complementary Output States
Common-Mode Output Voltage
Δ|V
OC
| for Complementary Output States
Output Short-Circuit Current
V
OUT
CMOS Input Logic Threshold Low
CMOS Input Logic Threshold High
Logic Input Current (DE, DI)
RECEIVER
Differential Input Threshold Voltage
Input Voltage Hysteresis
Input Resistance
Input Current (A, B)
Logic Enable Input Current (RE)
CMOS Output Voltage Low
CMOS Output Voltage High
Short-Circuit Output Current
Three-State Output Leakage Current
POWER SUPPLY CURRENT
V
OC
Min
Typ
Max
5.0
5.0
5.0
5.0
0.2
3.0
0.2
250
0.8
±1.0
V
TH
ΔV
TH
−0.2
70
12
1
−0.8
±1
0.4
4.0
7
85
±1.0
30
37
60
74
+0.2
Unit
V
V
V
V
V
V
V
mA
V
V
µA
V
mV
kΩ
mA
mA
µA
V
V
mA
µA
µA
µA
Test Conditions/Comments
R = ∞, see Figure 11
V
CC
= 5 V, R = 50 Ω (RS-422), see Figure 11
R = 27 Ω (RS-485), see Figure 11
V
TST
= –7 V to +12 V, see Figure 12, V
CC
= 5 V ± 5%
R = 27 Ω or 50 Ω, see Figure 11
R = 27 Ω or 50 Ω, see Figure 11
R = 27 Ω or 50 Ω
−7 V ≤ V
O
≤ +12 V
V
INL
V
INH
2.0
1.4
1.4
−7 V ≤ V
CM
≤ +12 V
V
CM
= 0 V
−7 V ≤ V
CM
≤ +12 V
V
IN
= 12 V
V
IN
= −7 V
I
OUT
= +4.0 mA
I
OUT
= −4.0 mA
V
OUT
= GND or V
CC
0.4 V ≤ V
OUT
≤ 2.4 V
Outputs unloaded, receivers enabled
DE = 0 V (disabled)
DE = 5 V (enabled)
V
OL
V
OH
I
CC
Rev. A | Page 3 of 16
ADM488A/ADM489A
TIMING SPECIFICATIONS
V
CC
= 5 V ± 10%. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
DRIVER
Propagation Delay Input to Output
Driver Output Skew
Driver Rise/Fall Time
Driver Enable to Output Valid
Driver Disable Timing
Maximum Data Rate
RECEIVER
Propagation Delay Input to Output
Skew
Receiver Enable
Receiver Disable
Maximum Data Rate
Symbol
t
PLH
, t
PHL
t
SKEW
t
DR
, t
DF
t
ZL
, t
ZH
t
LZ
, t
HZ
250
250
300
250
250
100
10
10
250
Min
250
100
Typ
Max
2000
800
2000
2000
3000
Unit
ns
ns
ns
ns
ns
kbps
ns
ns
ns
ns
kbps
Test Conditions/Comments
R
L
differential = 54 Ω, C
L1
= C
L2
= 100 pF, see
Figure 15, Figure 16
R
L
differential = 54 Ω, C
L1
= C
L2
= 100 pF, see
Figure 15
R
L
differential = 54 Ω, C
L1
= C
L2
= 100 pF, see
Figure 15, Figure 16
R
L
= 500 Ω, C
L
= 100 pF, see Figure 12, Figure 18
R
L
= 500 Ω, C
L
= 15 pF, see Figure 12, Figure 18
t
PLH
, t
PHL
|t
PLH
− t
PHL
|
t
EN1
t
EN2
2000
50
50
C
L
= 15 pF, see Figure 15, Figure 17
R
L
= 1 kΩ, C
L
= 15 pF, see Figure 14, Figure 19
R
L
= 1 kΩ, C
L
= 15 pF, see Figure 14, Figure 19
Rev. A | Page 4 of 16
嵌入式系统
