Changes to Figure 35 to Figure 40 ................................................ 12
Changes to Figure 44 ...................................................................... 15
10/2014—Revision 0: Initial Version
Rev. B | Page 2 of 23
Data Sheet
SPECIFICATIONS
ADM7154
V
IN
= V
OUT
+ 0.5 V or 2.3 V, whichever is greater; EN = V
IN
; I
LOAD
= 10 mA; C
IN
= C
OUT
= C
REG
= 10 µF; C
REF
= C
BYP
= 1 µF; T
A
= 25°C for
typical specifications; T
J
= −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.
Table 2.
Parameter
INPUT VOLTAGE RANGE
LOAD CURRENT
OPERATING SUPPLY CURRENT
SHUTDOWN CURRENT
NOISE
Output Noise
Noise Spectral Density
POWER SUPPLY REJECTION RATIO
Symbol
V
IN
I
LOAD
I
GND
I
IN_SD
OUT
NOISE
OUT
NSD
PSRR
Test Conditions/Comments
Min
2.3
Typ
Max
5.5
600
7.0
10
2
Unit
V
mA
mA
mA
µA
µV rms
µV rms
nV/√Hz
dB
dB
dB
dB
+0.5
+1.5
+2.0
+0.02
0.3
22
960
80
120
550
33
620
400
1.2
0.55
0.44
150
15
1.6
%
%
%
%/V
%/A
mA
mA
mV
mV
Ω
kΩ
Ω
Ω
ms
ms
ms
°C
°C
I
LOAD
= 0 µA
I
LOAD
= 600 mA
EN = GND
10 Hz to 100 kHz, V
OUT
= 1.2 V to 3.3 V
100 Hz to 100 kHz, V
OUT
= 1.2 V to 3.3 V
10 kHz to 1 MHz, V
OUT
= 1.2 V to 3.3 V
200 Hz to 200 kHz, V
IN
= 3.8 V, V
OUT
= 3.3 V,
I
LOAD
= 400 mA
1 MHz, V
IN
= 3.8 V, V
OUT
= 3.3 V, I
LOAD
= 400 mA
200 Hz to 200 kHz, V
IN
= 2.3 V, V
OUT
= 1.8 V,
I
LOAD
= 400 mA
1 MHz, V
IN
= 2.3 V, V
OUT
= 1.8 V, I
LOAD
= 400 mA
V
OUT
= V
REF
I
LOAD
= 10 mA, T
J
= +25°C
1 mA < I
LOAD
< 600 mA, T
J
= −40°C to +85°C
1 mA < I
LOAD
< 600 mA
V
IN
= V
OUT
+ 0.5 V or 2.3 V, whichever is greater,
to 5.5 V
I
OUT
= 1 mA to 600 mA
4.0
6.5
0.2
1.6
0.9
1.5
90
58
90
63
−0.5
−2.0
−2.0
−0.02
OUTPUT VOLTAGE ACCURACY
Initial Accuracy
V
OUT
REGULATION
Line
Load
1
CURRENT-LIMIT THRESHOLD
2
V
REF
V
OUT
DROPOUT VOLTAGE
3
PULL-DOWN RESISTANCE
VOUT
REG
REF
BYP
START-UP TIME
4
V
OUT
V
REG
V
REF
THERMAL SHUTDOWN
Threshold
Hysteresis
UNDERVOLTAGE THRESHOLDS
Input Voltage
Rising
Falling
Hysteresis
∆V
OUT
/∆V
IN
∆V
OUT
/∆I
OUT
I
LIMIT
700
V
DROPOUT
I
OUT
= 400 mA, V
OUT
= 3.3 V
I
OUT
= 600 mA, V
OUT
= 3.3 V
EN = 0 V, V
OUT
= 1 V, V
IN
= 5.5 V
EN = 0 V, V
REG
= 1 V, V
IN
= 5.5 V
EN = 0 V, V
REF
= 1 V, V
IN
= 5.5 V
EN = 0 V, V
BYP
= 1 V, V
IN
= 5.5 V
V
OUT
= 3.3 V
V
OUT
= 3.3 V
V
OUT
= 3.3 V
T
J
rising
1200
130
210
V
OUT_PULL
V
REG_PULL
V
REF_PULL
V
BYP_PULL
t
STARTUP
t
REG_STARTUP
t
REF_STARTUP
TS
SD
TS
SD_HYS
UVLO
RISE
UVLO
FALL
UVLO
HYS
2.29
1.95
200
V
V
mV
Rev. B | Page 3 of 23
ADM7154
Parameter
V
REG
THRESHOLDS
5
Rising
Falling
Hysteresis
PRECISION EN INPUT
Logic High
Logic Low
Logic Hysteresis
Leakage Current
1
2
Data Sheet
Symbol
V
REG_UVLORISE
V
REG_UVLOFALL
V
REG_UVLOHYS
2.3 V ≤ V
IN
≤ 5.5 V
EN
HIGH
EN
LOW
EN
HYS
I
EN_LKG
1.13
1.05
EN = V
IN
or GND
1.22
1.13
90
0.01
1.31
1.22
1
V
V
mV
µA
Test Conditions/Comments
Min
Typ
Max
1.94
1.60
185
Unit
V
V
mV
Based on an endpoint calculation using 1 mA and 600 mA loads.
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
3
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. Dropout applies only for output
voltages above 2.3 V.
4
Start-up time is defined as the time between the rising edge of V
EN
to V
OUT
, V
REG
, or V
REF
being at 90% of the nominal value.
5
The output voltage is disabled until the V
REG
UVLO rise threshold is crossed. The V
REG
output is disabled until the input voltage UVLO rising threshold is crossed.
Table 3. Input and Output Capacitors, Recommended Specifications
Parameter
MINIMUM CAPACITANCE
Input
1
Regulator
1
Output
1
Bypass
Reference
CAPACITOR ESR
C
REG
, C
OUT
, C
IN
, C
REF
C
BYP
1
Symbol
C
IN
C
REG
C
OUT
C
BYP
C
REF
R
ESR
R
ESR
Test Conditions/Comments
T
A
= −40°C to +125°C
T
A
= −40°C to +125°C
T
A
= −40°C to +125°C
T
A
= −40°C to +125°C
T
A
= −40°C to +125°C
T
A
= −40°C to +125°C
T
A
= −40°C to +125°C
Min
7.0
7.0
7.0
0.1
0.7
0.001
0.001
Typ
Max
Unit
µF
µF
µF
µF
µF
0.2
2.0
Ω
Ω
The minimum input, regulator, and output capacitances must be greater than 7.0 μF over the full range of operating conditions. The full range of operating conditions
in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are
recommended; Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. B | Page 4 of 23
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
VIN to GND
VREG to GND
VOUT to GND
BYP to VOUT
EN to GND
BYP to GND
REF to GND
REF_SENSE to GND
Storage Temperature Range
Junction Temperature
Operating Ambient Temperature
Range
Soldering Conditions
Rating
−0.3 V to +7 V
−0.3 V to VIN, or +4 V
(whichever is less)
−0.3 V to VREG, or +4 V
(whichever is less)
±0.3 V
−0.3 V to +7 V
−0.3 V to VREG, or +4 V
(whichever is less)
−0.3 V to VREG, or +4 V
(whichever is less)
−0.3 V to +4 V
−65°C to +150°C
150°C
−40°C to +125°C
JEDEC J-STD-020
ADM7154
Junction-to-ambient thermal resistance (θ
JA
) of the package is
based on modeling and calculation using a 4-layer PCB. The
junction-to-ambient thermal resistance is highly dependent on
the application and PCB layout. In applications where high
maximum power dissipation exists, close attention to thermal
PCB design is required. The value of θ
JA
can vary, depending on
PCB material, layout, and environmental conditions. The
specified values of θ
JA
are based on a 4-layer, 4 in. × 3 in. circuit
board. See JESD51-7 and JESD51-9 for detailed information on
the board construction.
Ψ
JB
is the junction-to-board thermal characterization parameter
with units of °C/W. Ψ
JB
of the package is based on modeling and
calculation using a 4-layer PCB. JESD51-12,
Guidelines for
Reporting and Using Electronic Package Thermal Information,
states that thermal characterization parameters are not the same
as thermal resistances. Ψ
JB
measures the component power
flowing through multiple thermal paths rather than a single
path as in thermal resistance, θ
JB
. Therefore, Ψ
JB
thermal paths
include convection from the top of the package as well as
radiation from the package, factors that make Ψ
JB
more useful
in real-world applications. Maximum junction temperature (T
J
)
is calculated from the PCB temperature (T
B
) and power
dissipation (P
D
) using the formula
T
J
=
T
B
+ (P
D
×
Ψ
JB
)
See JESD51-8 and JESD51-12 for more detailed information
about Ψ
JB
.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The
ADM7154
can be damaged when the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that T
J
is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temper-
ature may need to be derated.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit provided
that the junction temperature is within specification limits. The
junction temperature (T
J
) of the device is dependent on the
ambient temperature (T
A
), the power dissipation of the device
(P
D
), and the junction-to-ambient thermal resistance of the
package (θ
JA
).
Maximum junction temperature (T
J
) is calculated from the
ambient temperature (T
A
) and power dissipation (P
D
) using the
following formula:
T
J
=
T
A
+ (P
D
×
θ
JA
)
THERMAL RESISTANCE
θ
JA
, θ
JC
, and Ψ
JB
are specified for the worst case conditions, that
is, a device soldered in a circuit board for surface-mount
