a
FEATURES
Six Direct Voltage Measurement Inputs (Including Two
Processor Core Voltages) with On-Chip Attenuators
On-Chip Temperature Sensor
Five Digital Inputs for VID Bits
Fully Supports Intel’s LANDesk Client Manager (LDCM)
Register-Compatible with LM7x Products
Two Fan Speed Monitoring Inputs
I
2
C
®
Compatible System Management Bus (SMBus)
Chassis Intrusion Detect
Interrupt Output
Programmable RESET I/O Pin
Shutdown Mode to Minimize Power Consumption
Limit Comparison of all Monitored Values
APPLICATIONS
Network Servers and Personal Computers
Microprocessor-Based Office Equipment
Test Equipment and Measuring Instruments
Low Cost Microprocessor
System Hardware Monitor
ADM9240
PRODUCT DESCRIPTION
The ADM9240 is a complete system hardware monitor for
microprocessor-based systems, providing measurement and
limit comparison of up to four power supplies and two proces-
sor core voltages, plus temperature, two fan speeds and chassis
intrusion. Measured values can be read out via an I
2
C-compat-
ible serial System Management Bus, and values for limit com-
parisons can be programmed in over the same serial bus. The
high speed successive approximation ADC allows frequent
sampling of all analog channels to ensure a fast interrupt
response to any out-of-limit measurement.
The ADM9240’s 2.85 V to 5.75 V supply voltage range, low
supply current and I
2
C compatible interface, make it ideal for a
wide range of applications. These include hardware monitoring
and protection applications in personal computers, electronic
test equipment and office electronics.
FUNCTIONAL BLOCK DIAGRAM
V
CC
VID0
VID1
VID2
VID3
VID4 AND
DEVICE ID
REGISTER
VID0 - 3 AND
FAN DIVISOR
REGISTERS
SERIAL BUS
ADDRESS
REGISTER
SERIAL BUS
INTERFACE
NTEST_OUT/A0
A1
SDA
SCL
VALUE AND LIMIT
REGISTERS
LIMIT
COMPARATORS
CI
INTERRUPT
STATUS
REGISTERS
INT
MASK
REGISTERS
INT
CONFIGURATION
REGISTER
VID4
FAN1
FAN2
FAN SPEED
COUNTER
ADDRESS
POINTER
REGISTER
TEMPERATURE
CONFIGURATION
REGISTER
+V
CCP1
+2.5V
IN
+3.3V
IN
+5V
IN
+12V
IN
+V
CCP2
BANDGAP
TEMPERATURE
SENSOR
INPUT
ATTENUATORS
AND
ANALOG
MULTIPLEXER
9-BIT ADC
ANALOG
OUTPUT REGISTER
AND 8-BIT DAC
NTEST_IN/AOUT
RESET
ADM9240
CHASSIS
INTRUSION
CLEAR REGISTER
GNDA
GNDD
I
2
C is a registered trademark of Philips Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
ADM9240–SPECIFICATIONS
1, 2
(T = T
A
MIN
to T
MAX
, V
CC
= V
MIN
to V
MAX
, unless otherwise noted)
Max
5.75
2.0
100
±
3
±
2
Units
V
mA
mA
µA
°C
°C
°C
Test Conditions/Comments
Parameter
POWER SUPPLY
Supply Voltage, V
CC
Supply Current, I
CC
Min
2.85
Typ
5
1.4
1.0
25
Interface Inactive, ADC Active
ADC Inactive, DAC Active
Shutdown Mode
–40°C
≤
T
A
≤
+125°C
T
A
= +25°C
TEMPERATURE-TO-DIGITAL CONVERTER
Accuracy
Resolution
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENUATORS)
Total Unadjusted Error, TUE
Differential Nonlinearity, DNL
Power Supply Sensitivity
Total Monitoring Cycle Time
Input Resistance
ANALOG OUTPUT
Output Voltage Range
Total Unadjusted Error, TUE
Full-Scale Error
Zero Error
Differential Nonlinearity, DNL
Integral Nonlinearity
Output Source Current
Output Sink Current
FAN RPM-TO-DIGITAL CONVERTER
Accuracy
Full-Scale Count
FAN1 and FAN2 Nominal Input RPM
100
0
±
1
2
±
1
2
1
±
0.5
±
1
311
311
140
±
2
±
1
331
353
200
1.25
±
3
±
3
±
1
%
LSB
%/V
µs
µs
kΩ
V
%
%
LSB
LSB
LSB
mA
mA
%
%
rpm
rpm
rpm
rpm
Note 3
+25°C
≤
T
A
≤
+125°C (Note 4)
–40°C
≤
T
A
≤
+125°C (Note 4)
I
L
= 2 mA
No Load
Monotonic by Design
±
6
±
12
255
8800
4400
2200
1100
+25°C
≤
T
A
≤
+125°C
–40
o
C
≤
T
A
≤
+125°C
Divisor = 1, Fan Count = 153
(Note 5)
Divisor = 2, Fan Count = 153
(Note 5)
Divisor = 3, Fan Count = 153
(Note 5)
Divisor = 4, Fan Count = 153
(Note 5)
+25°C
≤
T
A
≤
+125°C
–40
o
C
≤
T
A
≤
+125°C
I
OUT
= 5.0 mA,
V
CC
= 4.25 V–5.75 V
I
OUT
= 3.0 mA,
V
CC
= 2.85 V–3.45 V
I
OUT
= –5.0 mA,
V
CC
= 4.25 V–5.75 V
I
OUT
= –3.0 mA,
V
CC
= 2.85 V–3.45 V
Internal Clock Frequency
DIGITAL OUTPUT NTEST_OUT
Output High Voltage, V
OH
21.1
19.8
2.4
2.4
22.5
22.5
23.9
25.2
kHz
kHz
V
V
Output Low Voltage, V
OL
0.4
0.4
V
V
OPEN-DRAIN DIGITAL OUTPUTS
(INT,
RESET,
CI)
Output Low Voltage, V
OL
High Level Output Current, I
OH
RESET
and CI Pulsewidth
20
0.1
45
0.4
0.4
100
V
V
µA
ms
I
OUT
= –5.0 mA, V
CC
= 5.75 V
I
OUT
= –3.0 mA, V
CC
= 3.45 V
V
OUT
= V
CC
–2–
REV. 0
ADM9240
Parameter
OPEN-DRAIN SERIAL DATA BUS
OUTPUT (SDA)
Output Low Voltage, V
OL
Min
Typ
Max
Units
Test Conditions/Comments
0.4
0.4
V
V
µA
High Level Output Current, I
OH
SERIAL BUS DIGITAL INPUTS
(SCL, SDA)
Input High Voltage, V
IH
Input Low Voltage, V
IL
Hysteresis
DIGITAL INPUT LOGIC LEVELS
(A0, A1, CI,
RESET,
VID0 – VID4,
FAN1, FAN2)
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input High Voltage, V
IH
Input Low Voltage, V
IL
NTEST_IN
Input High Voltage, V
IH
Input High Voltage, V
IH
DIGITAL INPUT CURRENT
Input High Current, I
IH
Input High Current, A0, A1, I
IH
Input Low Current, I
IL
Input Capacitance, C
IN
SERIAL BUS TIMING
7
Clock Frequency, f
SCLK
Glitch Immunity, t
SW
Bus Free Time, t
BUF
Start Setup Time, t
SU;STA
Start Hold Time, t
HD;STA
SCL Low Time, t
LOW
SCL High Time, t
HIGH
SCL, SDA Rise Time, t
R
SCL, SDA Fall Time, t
F
Data Setup Time, t
SU;DAT
Data Hold Time, t
HD;DAT
0.1
100
I
OUT
= –3.0 mA,
V
CC
= 4.25 V–5.75 V
I
OUT
= –3.0 mA
V
CC
= 2.85 V–3.45 V
V
OUT
= V
CC
0.7
×
V
CC
500
0.3
×
V
CC
V
V
mV
2.4
0.8
2.0
0.4
2.4
2.0
–1
–200
V
V
V
V
V
V
µA
µA
µA
pF
kHz
ns
µs
ns
ns
µs
µs
ns
µs
ns
ns
V
CC
= 4.25 V–5.75 V
V
CC
= 4.25 V–5.75 V
V
CC
= 2.85 V–3.45 V
V
CC
= 2.85 V–3.45 V
V
CC
= 4.25 V–5.75 V
V
CC
= 2.85 V–3.45 V
V
IN
= V
CC
V
IN
= V
CC
(Note 6)
V
IN
= 0
75
1
20
400
50
1.3
600
600
1.3
0.6
300
300
100
900
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
NOTES
1
All voltages are measured with respect to GND, unless otherwise noted.
2
Typicals are at T
A
= +25°C and represent most likely parametric norm. Shutdown current typ is measured with V
CC
= 3.3 V.
3
TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC, multiplexer and on-chip input attenuators, including an external series input
protection resistor value between zero and 1 kΩ.
4
Total monitoring cycle time is the time taken to measure all six analog inputs plus the temperature sensor.
5
The total fan count is based on 2 pulses per revolution of the fan tachometer output.
6
A0 and A1 have internal 75 kΩ pull-down.
7
Timing specifications are tested at logic levels of V
IL
= 0.3
×
V
CC
for a falling edge and V
IH
= 0.7
×
V
CC
for a rising edge.
Specifications subject to change without notice.
REV. 0
–3–
ADM9240
ABSOLUTE MAXIMUM RATINGS*
Positive Supply Voltage (V
CC
) . . . . . . . . . . . . . . . . . . . . . 6.5 V
Voltage on Any Input or Output Pin . . –0.3 V to (V
CC
+ 0.3 V)
(Except Analog Inputs)
16 V V
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16 V
All Other Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . +7.5 V
Ground Difference (GNDD–GNDA) . . . . . . . . . . . .
±
300 mV
Input Current At Any Pin . . . . . . . . . . . . . . . . . . . . . . .
±
5 mA
Package Input Current . . . . . . . . . . . . . . . . . . . . . . . .
±
20 mA
Maximum Junction Temperature (T
J
max) . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering
Vapor Phase 60 (sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared 15 (sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +200°C
ESD Rating All Pins Except Pin 15 . . . . . . . . . . . . . . . . 2000 V
ESD Rating Pin 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 V
Start
Condition
(S)
Bit 7
MSB
(A7)
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
24-Lead Small Outline Package:
θ
JA
= 50°C/Watt,
θ
JC
= 10°C/Watt
ORDERING GUIDE
Temperature
Range
–40°C to +125°C
Package
Description
Package
Option
Model
ADM9240ARU
24-Lead TSSOP RU-24
PIN CONFIGURATION
Bit 6
(A6)
NTEST_OUT/A0
A1
SDA
PROTOCOL
t
SU;STA
SCL
t
LOW
t
HIGH
1/f
SCL
1
2
3
4
5
6
24
23
22
21
VID0
VID1
VID2
VID3
VID4
t
BUF
SDA
t
r
t
f
SCL
FAN1
FAN2
ADM9240
20
t
HD;STA
Bit 0
LSB
(R/W)
t
SU;DAT
Stop
Condition
(P)
t
HD;DAT
CI
GNDD
+V
CCP1
TOP VIEW
19
(Not to Scale)
18
+2.5V
7
IN
8
9
10
11
17
+3.3V
IN
16
+5V
IN
15
+12V
IN
14
+V
CCP2
13
GNDA
PROTOCOL
Acknowledge
(A)
V
CC
INT
NTEST_IN/AOUT
SCL
RESET
12
SDA
t
VD;DAT
t
SU;STO
Figure 1. Diagram for Serial Bus Timing
–4–
REV. 0
ADM9240
PIN FUNCTION DESCRIPTIONS
Pin Number
1
2
3
4
5
6
7
Mnemonic
NTEST_OUT/A0
A1
SDA
SCL
FAN1
FAN2
CI
Description
Digital I/O. Dual Function Pin. The lowest order programmable bit of the Serial Bus Address.
This pin functions as an output when doing a NAND Tree test.
Digital Input. The highest order programmable bit of the Serial Bus Address.
Digital I/O. Serial Bus Bidirectional Data. Open-drain output.
Digital Input. Serial Bus Clock.
Digital Input. 0 to V
CC
amplitude fan tachometer input.
Digital Input. 0 to V
CC
amplitude fan tachometer input.
Digital I/O. An active high input from an external circuit that latches a Chassis Intrusion
event. This line can go high without any clamping action regardless of the powered state of
the ADM9240. The ADM9240 provides an internal open drain on this line, controlled by
Bit 6 of Register 40h or Bit 7 of Register 46h, to provide a minimum 20 ms pulse on this line,
to reset the external Chassis Intrusion Latch.
Digital Ground. Internally connected to all of the digital circuitry.
Power (+2.85 V to +5.75 V). Typically powered from +3.3 V or +5 V power rail. Bypass with
the parallel combination of 10
µF
(electrolytic or tantalum) and 0.1
µF
(ceramic) bypass
capacitors.
Digital Output. Interrupt Request (open drain). The output is enabled when Bit 1 of the
Configuration Register is set to 1. The default state is disabled.
Digital Input/Analog Output. An active-high input that enables NAND Tree mode board-
level connectivity testing. Refer to section on NAND Tree testing. Also functions as a pro-
grammable analog output when NAND Tree is not selected
Digital I/O. Master Reset, 5 mA driver (open drain), active low output with a 20 ms minimum
pulsewidth. Available when enabled via Bit 7 in Register 44h, and set using Bit 4 in Register
40h. Also acts as reset input when pulled low (e.g., power-on reset).
Analog Ground. Internally connected to all analog circuitry. The ground reference for all
analog inputs.
Analog Input. Monitors processor core voltage +V
CCP2
(0 V–3.6 V). Can also be used to
monitor the –12 V supply by adding two external resistors.
Analog Input. Monitors +12 V supply.
Analog Input. Monitors +5 V supply.
Analog Input. Monitors +3.3 V supply.
Analog Input. Monitors +2.5 V supply.
Analog Input. Monitors processor core voltage +V
CCP1
(0 V–3.6 V).
Digital Input. Core Voltage ID readouts from the processor. This value is read into the
VID4 Status Register.
Digital Input. Core Voltage ID readouts from the processor. This value is read into the
VID0–VID3 Status Register.
Digital Input. Core Voltage ID readouts from the processor. This value is read into the
VID0–VID3 Status Register.
Digital Input. Core Voltage ID readouts from the processor. This value is read into the
VID0–VID3 Status Register.
Digital Input. Core Voltage ID readouts from the processor. This value is read into the
VID0–VID3 Status Register.
8
9
GNDD
V
CC
INT
NTEST_IN/AOUT
10
11
12
RESET
13
14
15
16
17
18
19
20
21
22
23
24
GNDA
+V
CCP2
+12 V
IN
+5 V
IN
+3.3 V
IN
+2.5 V
IN
+V
CCP1
VID4
VID3
VID2
VID1
VID0
REV. 0
–5–
