Changes to Ordering Guide ...........................................................17
5/10—Rev. A to Rev. B
Changes to Figure 1 .......................................................................... 1
4/10—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 17
2/10—Revision 0: Initial Version
Rev. E | Page 2 of 20
Data Sheet
SPECIFICATIONS
ADP172
V
IN
= (V
OUT
+ 0.4 V) or 1.6 V (whichever is greater), EN = V
IN
, I
OUT
= 10 mA, C
IN
= C
OUT
= 1 µF, T
A
= 25°C, unless otherwise noted.
Table 1.
Parameter
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT
1
Symbol
V
IN
I
GND
Conditions
T
J
= −40°C to +125°C
I
OUT
= 0 µA
I
OUT
= 0 µA, T
J
= −40°C to +125°C
I
OUT
= 1 mA
I
OUT
= 1 mA, T
J
= −40°C to +125°C
I
OUT
= 150 mA
I
OUT
= 150 mA, T
J
= −40°C to +125°C
I
OUT
= 300 mA
I
OUT
= 300 mA, T
J
= −40°C to +125°C
EN = GND
EN = GND, V
IN
= 3.6 V, T
J
= −40°C to +85°C
EN = GND, V
IN
= 3.6 V, T
J
= 85°C to 125°C
I
OUT
= 10 mA
1 mA < I
OUT
< 300 mA, V
IN
= (V
OUT
+ 0.5 V) to 3.6 V
1 mA < I
OUT
< 300 mA, V
IN
= (V
OUT
+ 0.5 V) to 3.6 V,
T
J
= −40°C to +125°C
V
IN
= (V
OUT
+ 0.5 V) to 3.6 V, T
J
= −40°C to +125°C
I
OUT
= 1 mA to 300 mA
I
OUT
= 1 mA to 300 mA, T
J
= −40°C to +125°C
I
OUT
= 10 mA, V
OUT
≥ 1.8 V
I
OUT
= 10 mA, V
OUT
≥ 1.8 V, T
J
= −40°C to +125°C
I
OUT
= 150 mA, V
OUT
≥ 1.8 V
I
OUT
= 150 mA, V
OUT
≥ 1.8 V, T
J
= −40°C to +125°C
I
OUT
= 300 mA, V
OUT
≥ 1.8 V
I
OUT
= 300 mA, V
OUT
≥ 1.8 V, T
J
= −40°C to +125°C
V
OUT
= 1.8 V
Min
1.6
Typ
23
60
50
100
130
210
170
260
0.1
2
25
+1
+1.5
+1.5
+0.25
0.001
0.005
2
7
25
50
50
100
400
T
J
rising
120
450
150
15
1.2
0.4
0.1
1
1.5
0.7
80
72
50
40
30
800
Max
3.6
Unit
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
%
%
%
%/V
%/mA
%/mA
mV
mV
mV
mV
mV
mV
µs
mA
°C
°C
V
V
µA
µA
V
V
mV
µV rms
µV rms
µV rms
µV rms
SHUTDOWN CURRENT
I
GND-SD
OUTPUT VOLTAGE ACCURACY
V
OUT
−1
−2
−3
−0.25
LINE REGULATION
LOAD REGULATION
2
DROPOUT VOLTAGE
3
∆V
OUT
/∆V
IN
∆V
OUT
/∆I
OUT
V
DROPOUT
START-UP TIME
CURRENT-LIMIT THRESHOLD
5
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
4
t
START-UP
I
LIMIT
TS
SD
TS
SD-HYS
V
IH
V
IL
V
I-LEAKAGE
UVLO
UVLO
RISE
UVLO
FALL
UVLO
HYS
OUT
NOISE
EN INPUT
Logic High Voltage
Logic Low Voltage
Leakage Current Voltage
UNDERVOLTAGE LOCKOUT
Input Voltage Rising
Input Voltage Falling
Hysteresis
OUTPUT NOISE
1.6 V ≤ V
IN
≤ 3.6 V
1.6 V ≤ V
IN
≤ 3.6 V
EN = VIN or GND
EN = VIN or GND, T
J
= −40°C to +125°C
T
J
= −40°C to +125°C
T
J
= −40°C to +125°C
10 Hz to 100 kHz, V
IN
= 3.6 V, V
OUT
= 3.0 V
10 Hz to 100 kHz, V
IN
= 3.6 V, V
OUT
= 1.8 V
10 Hz to 100 kHz, V
IN
= 3.6 V, V
OUT
= 1.2 V
10 Hz to 100 kHz, V
IN
= 3.6 V, V
OUT
= 0.8 V
Rev. E | Page 3 of 20
ADP172
Parameter
POWER SUPPLY REJECTION RATIO
Symbol
PSRR
Conditions
1 kHz, V
IN
= 3.6 V, I
OUT
= 10 mA, V
OUT
= 0.8 V
10 kHz, V
IN
= 3.6 V, I
OUT
= 10 mA, V
OUT
= 0.8 V
10 kHz, V
IN
= (V
OUT
+ 1 V), I
OUT
= 10 mA to 300 mA
100 kHz, V
IN
= (V
OUT
+ 1 V), I
OUT
= 10 mA to 300 mA
Min
Typ
73
70
50
47
Data Sheet
Max
Unit
dB
dB
dB
dB
The current from the external resistor divider network in the case of adjustable voltage output (as with the
ADP172)
should be subtracted from the ground current measured.
Based on an end-point calculation using 1 mA and 300 mA loads. See Figure 4 for typical load regulation performance for loads less than 1 mA.
3
Applies only for output voltages above 1.6 V. Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal
output voltage.
4
Start-up time is defined as the time between the rising edge of EN and VOUT at 90% of its nominal value.
5
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
1
2
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter
MINIMUM INPUT AND OUTPUT
CAPACITANCE
1
CAPACITOR ESR
1
Symbol
C
MIN
R
ESR
Conditions
T
J
= −40°C to +125°C
T
J
= −40°C to +125°C
Min
0.45
0.001
Typ
Max
Unit
µF
Ω
1
The minimum input and output capacitance should be greater than 0.45 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. E | Page 4 of 20
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
VOUT to GND
EN to GND
Storage Temperature Range
Operating Junction Temperature Range
Operating Ambient Temperature Range
Soldering Conditions
Rating
−0.3 V to +4.0 V
−0.3 V to VIN
−0.3 V to +4.0 V
−65°C to +150°C
−40°C to +125°C
−40°C to +85°C
JEDEC J-STD-020
ADP172
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
JA
may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θ
JA
are based on a 4-layer, 4 in. × 3 in. PCB.
Refer to JESD51-7 for detailed information regarding board
construction.
Ψ
JB
is the junction-to-board thermal characterization parameter
with units of °C/W. The Ψ
JB
of the package is based on modeling
and calculation using a 4-layer board. The
Guidelines for Reporting
and Using Electronic Package Thermal Information: JESD51-12
states that thermal characterization parameters are not the same
as thermal resistances. Ψ
JB
measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θ
JB
. Therefore, Ψ
JB
thermal paths include
convection from the top of the package as well as radiation from
the package—factors that make Ψ
JB
more useful in real-world
applications. Maximum junction temperature (T
J
) is calculated
from the board temperature (T
B
) and power dissipation (P
D
)
using the formula
T
J
=
T
B
+ (P
D
×
Ψ
JB
)
Refer to JESD51-8 and JESD51-12 for more detailed information
about Ψ
JB
.
Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply only individually, not in
combination. The
ADP172
can be damaged when the junction
temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that T
J
is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temperature
may have to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (T
J
) of
the device is dependent on the ambient temperature (T
A
), the
power dissipation of the device (P
D
), and the junction-to-
ambient thermal resistance of the package (θ
JA
).
Maximum junction temperature (T
J
) is calculated from the
ambient temperature (T
A
) and power dissipation (P
D
) using the
following formula:
T
J
=
T
A
+ (P
D
×
θ
JA
)
Junction-to-ambient thermal resistance (θ
JA
) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
THERMAL RESISTANCE
θ
JA
and Ψ
JB
are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
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