Data Sheet
FEATURES
Synchronous Buck Controller with Constant
On-Time and Valley Current Mode
ADP1874/ADP1875
TYPICAL APPLICATIONS CIRCUIT
V
IN
= 2.95V TO 20V
VIN
C
C2
Power input voltage range: 2.95 V to 20 V
On-board bias regulator
Minimum output voltage: 0.6 V
0.6 V reference voltage with ±1.0% accuracy
Supports all N-channel MOSFET power stages
Available in 300 kHz, 600 kHz, and 1.0 MHz options
No current-sense resistor required
Power saving mode (PSM) for light loads (ADP1875 only)
Resistor programmable current limit
Power good with internal pull-up resistor
Externally programmable soft start
Thermal overload protection
Short-circuit protection
Standalone precision enable input
Integrated bootstrap diode for high-side drive
Starts into a precharged output
Available in a 16-lead QSOP package
C
C
R
C
VREG
V
OUT
ADP1874/
ADP1875
COMP
BST
C
BST
EN
FB
DRVH
SW
DRVL
C
IN
10kΩ
R
TOP
R
BOT
Q1
L
V
OUT
GND
C
VREG2
C
VREG
R
RES
C
OUT
Q2
R
PGD
C
SS
R
TRK2
R
TRK1
LOAD
VREG PGOOD
SS
VREG_IN
RES
TRACK
PGND
V
EXT
V
MASTER
09347-001
Figure 1. Typical Applications Circuit
100
95
90
85
80
75
70
65
60
55
50
45
40 V
IN
= 16.5V (PSM)
35
30
25
10
100
V
IN
= 13V (PSM)
T
A
= 25°C
V
OUT
= 1.8V
f
SW
= 300kHz
WÜRTH INDUCTOR:
744325120, L = 1.2µH, DCR = 1.8mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
1k
LOAD CURRENT (mA)
10k
100k
09347-102
V
IN
= 5V (PSM)
APPLICATIONS
EFFICIENCY (%)
Telecom and networking systems
Mid- to high-end servers
Set-top boxes
DSP core power supplies
V
IN
= 16.5V
V
IN
= 13V
GENERAL DESCRIPTION
The
ADP1874/ADP1875
are versatile current mode, synchronous
step-down controllers. They provide superior transient response,
optimal stability, and current-limit protection by using a constant
on-time, pseudo fixed frequency with a programmable current
limit, current control scheme. In addition, these devices offer
optimum performance at low duty cycles by using a valley, current
mode control architecture. This allows the
ADP1874/ADP1875
to drive all N-channel power stages to regulate output voltages
to as low as 0.6 V.
The
ADP1875
is the power saving mode (PSM) version of
the device and is capable of pulse skipping to maintain output
regulation while achieving improved system efficiency at light
loads (see the ADP1875 Power Saving Mode (PSM) section for
more information).
Available in three frequency options (300 kHz, 600 kHz, and
1.0 MHz, plus the PSM option), the
ADP1874/ADP1875
are well
suited for a wide range of applications that require a single-input
power supply range from 2.95 V to 20 V. Low voltage biasing is
supplied via a 5 V internal low dropout regulator (LDO).
Figure 2.
ADP1874/ADP1875
Efficiency vs. Load Current (V
OUT
= 1.8 V, 300 kHz)
In addition, soft start programmability is included to limit input
in-rush current from the input supply during startup and to
provide reverse current protection during precharged output
conditions. The low-side current sense, current gain scheme, and
integration of a boost diode, along with the PSM/forced pulse-
width modulation (PWM) option, reduce the external part count
and improve efficiency.
The
ADP1874/ADP1875
operate over the −40°C to +125°C
junction temperature range and are available in a 16-lead QSOP
package.
Rev. A
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Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
ADP1874/ADP1875
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Typical Applications Circuit............................................................ 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
Boundary Condition .................................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
ADP1874/ADP1875 Block Digram ............................................... 18
Theory of Operation ...................................................................... 19
Startup .......................................................................................... 19
Soft Start ...................................................................................... 19
Precision Enable Circuitry ........................................................ 19
Undervoltage Lockout ............................................................... 19
On-Board Low Dropout Regulator .......................................... 20
Thermal Shutdown ..................................................................... 20
Programming Resistor (RES) Detect Circuit.......................... 20
Valley Current-Limit Setting .................................................... 20
Hiccup Mode During Short Circuit ......................................... 22
Synchronous Rectifier ................................................................ 22
ADP1875 Power Saving Mode (PSM) ...................................... 22
Data Sheet
Timer Operation ........................................................................ 23
Pseudo-Fixed Frequency ........................................................... 24
Power Good Monitoring ........................................................... 24
Voltage Tracking ......................................................................... 25
Applications Information .............................................................. 27
Feedback Resistor Divider ........................................................ 27
Inductor Selection ...................................................................... 27
Output Ripple Voltage (ΔV
RR
) .................................................. 27
Output Capacitor Selection....................................................... 27
Compensation Network ............................................................ 28
Efficiency Consideration ........................................................... 29
Input Capacitor Selection .......................................................... 30
Thermal Considerations............................................................ 31
Design Example .......................................................................... 32
External Component Recommendations .................................... 34
Layout Considerations ................................................................... 36
IC Section (Left Side of Evaluation Board) ............................. 38
Power Section ............................................................................. 38
Differential Sensing .................................................................... 39
Typical Application Circuits ......................................................... 40
12 A, 300 kHz High Current Application Circuit .................. 40
5.5 V Input, 600 kHz Application Circuit ............................... 40
300 kHz High Current Application Circuit ............................ 41
Outline Dimensions ....................................................................... 42
Ordering Guide .......................................................................... 42
REVISION HISTORY
7/12—Rev. 0 to Rev. A
Changes to Table 7 .......................................................................... 21
3/11—Revision 0: Initial Version
Rev. A | Page 2 of 44
Data Sheet
SPECIFICATIONS
ADP1874/ADP1875
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VREG = 5 V,
BST − SW = VREG − V
RECT_DROP
(see Figure 40 to Figure 42). V
IN
= 12 V. The specifications are valid for T
J
= −40°C to +125°C,
unless otherwise specified.
Table 1.
Parameter
POWER SUPPLY CHARACTERISTICS
High Input Voltage Range
Symbol
VIN
Test Conditions/Comments
C
VIN
= 22 µF(25 V rating) to PGND (at Pin 1)
ADP1874ARQZ-0.3/ADP1875ARQZ-0.3 (300 kHz)
ADP1874ARQZ-0.6/ADP1875ARQZ-0.6 (600 kHz)
ADP1874ARQZ-1.0/ADP1875ARQZ-1.0 (1.0 MHz)
FB = 1.5 V, no switching
EN < 600 mV
Rising V
IN
(see Figure 35 for temperature variation)
Falling V
IN
from operational state
VREG and VREG_IN tied together and should not be
loaded externally because they are intended to only
bias internal circuitry
C
VREG
= 4.7 µF to PGND, 0.22 µF to GND, V
IN
= 2.95 V to 20 V
ADP1874ARQZ-0.3/ADP1875ARQZ-0.3 (300 kHz)
ADP1874ARQZ-0.6/ADP1875ARQZ-0.6 (600 kHz)
ADP1874ARQZ-1.0/ADP1875ARQZ-1.0 (1.0 MHz)
V
IN
= 7 V, 100 mA
V
IN
= 12 V, 100 mA
0 mA to 100 mA, V
IN
= 7 V
0 mA to 100 mA, V
IN
= 20 V
V
IN
= 7 V to 20 V, 20 mA
V
IN
= 7 V to 20 V, 100 mA
100 mA out of VREG, V
IN
≤ 5 V
V
IN
= 20 V
Connect external capacitor from SS pin to GND,
C
SS
= 10 nF/ms
V
FB
T
J
= 25°C
T
J
= −40°C to +85°C
T
J
= −40°C to +125°C
FB = 0.6 V, EN = VREG
RES = 47 kΩ ± 1%
RES = 22 kΩ ± 1%
RES = none
RES = 100 kΩ ± 1%
Typical values measured at 50% time points with
0 nF at DRVH and DRVL; maximum values are
guaranteed by bench evaluation
1
2.7
5.5
11
22
Min
Typ
Max
Unit
2.95
2.95
3.25
Quiescent Current
Shutdown Current
Undervoltage Lockout
UVLO Hysteresis
INTERNAL REGULATOR
CHARACTERISTICS
VREG Operational Output Voltage
I
Q_REG
+ I
Q_BST
I
REG,SD
+ I
BST,SD
UVLO
12
12
12
1.1
140
2.65
190
20
20
20
225
V
V
V
mA
µA
V
mV
VREG
VREG Output in Regulation
Load Regulation
Line Regulation
VIN to VREG Dropout Voltage
Short VREG to PGND
SOFT START
Soft Start Period Calculation
ERROR AMPLIFER
FB Regulation Voltage
2.75
2.75
3.05
4.82
4.83
5
5
5
4.981
4.982
32
34
2.5
2
300
229
10
5.5
5.5
5.5
5.16
5.16
415
320
V
V
V
V
V
mV
mV
mV
mV
mV
mA
nF/ms
Transconductance
FB Input Leakage Current
CURRENT-SENSE AMPLIFIER GAIN
Programming Resistor (RES)
Value from RES to PGND
G
m
I
FB, LEAK
596
594.2
320
600
600
600
496
1
3
6
12
24
604
605.8
670
50
3.3
6.5
13
26
mV
mV
mV
µS
nA
V/V
V/V
V/V
V/V
SWITCHING FREQUENCY
ADP1874ARQZ-0.3/
ADP1875ARQZ-0.3 (300 kHz)
On-Time
Minimum On-Time
Minimum Off-Time
300
VIN = 5 V, V
OUT
= 2 V, T
J
= 25°C
VIN = 20 V
84% duty cycle (maximum)
Rev. A | Page 3 of 44
kHz
1280
190
400
ns
ns
ns
1120
1200
145
340
ADP1874/ADP1875
Parameter
ADP1874ARQZ-0.6/
ADP1875ARQZ-0.6 (600 kHz)
On-Time
Minimum On-Time
Minimum Off-Time
ADP1874ARQZ-1.0/
ADP1875ARQZ-1.0 (1.0 MHz)
On-Time
Minimum On-Time
Minimum Off-Time
OUTPUT DRIVER CHARACTERISTICS
High-Side Driver
Output Source Resistance
2
Output Sink Resistance
2
Rise Time
3
Fall Time
3
Low-Side Driver
Output Source Resistance
2
Output Sink Resistance
2
Rise Time
3
Fall Time
3
Propagation Delays
DRVL Fall to DRVH Rise
3
DRVH Fall to DRVL Rise
3
SW Leakage Current
Integrated Rectifier
Channel Impedance
PRECISION ENABLE THRESHOLD
Logic High Level
Enable Hysteresis
COMP VOLTAGE
COMP Clamp Low Voltage
COMP Clamp High Voltage
COMP Zero Current Threshold
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
CURRENT LIMIT
Hiccup Current Limit Timing
OVERVOLTAGE AND POWER GOOD
THRESHOLDS
FB Power Good Threshold
FB Power Good Hysteresis
FB Overvoltage Threshold
FB Overvoltage Hysteresis
PGOOD Low Voltage During Sink
PGOOD Leakage Current
Symbol
Test Conditions/Comments
Min
Typ
600
540
82
340
1.0
312
52
340
Data Sheet
Max
Unit
kHz
ns
ns
ns
MHz
ns
ns
ns
VIN = 5 V, V
OUT
= 2 V, T
J
= 25°C
VIN = 20 V, V
OUT
= 0.8 V
65% duty cycle (maximum)
500
580
110
400
VIN = 5 V, V
OUT
= 2 V, T
J
= 25°C
VIN = 20 V
45% duty cycle (maximum)
285
340
85
400
t
r, DRVH
t
f, DRVH
I
SOURCE
= 1.5 A, 100 ns, positive pulse (0 V to 5 V)
I
SINK
= 1.5 A, 100 ns, negative pulse (5 V to 0 V)
BST − SW = 4.4 V, C
IN
= 4.3 nF (see Figure 59)
BST − SW = 4.4 V, C
IN
= 4.3 nF (see Figure 60)
I
SOURCE
= 1.5 A, 100 ns, positive pulse (0 V to 5 V)
I
SINK
= 1.5 A, 100 ns, negative pulse (5 V to 0 V)
VREG = 5.0 V, C
IN
= 4.3 nF (see Figure 60)
VREG = 5.0 V, C
IN
= 4.3 nF (see Figure 59)
BST − SW = 4.4 V (see Figure 59)
BST − SW = 4.4 V (see Figure 60)
BST = 25 V, SW = 20 V, VREG = 5 V
I
SINK
= 10 mA
VIN = 2.9 V to 20 V, VREG = 2.75 V to 5.5 V
VIN = 2.9 V to 20 V, VREG = 2.75 V to 5.5 V
570
2.25
0.70
25
11
1.6
0.7
18
16
15.4
18
3.5
1
Ω
Ω
ns
ns
Ω
Ω
ns
ns
ns
ns
µA
Ω
2.4
1
t
r,DRVL
t
f,DRVL
t
tpdhDRVH
t
tpdhDRVL
I
SWLEAK
110
22
630
31
680
mV
mV
V
V
COMP(LOW)
V
COMP(HIGH)
V
COMP_ZCT
T
TMSD
Tie EN pin to VREG to enable device
(2.75 V ≤ VREG ≤ 5.5 V)
(2.75 V ≤ VREG ≤ 5.5 V)
(2.75 V ≤ VREG ≤ 5.5 V)
Rising temperature
0.47
2.55
1.15
155
15
6
V
V
°C
°C
ms
COMP = 2.4 V
PGOOD
FB
PGD
FB
OV
V
PGOOD
V
FB
rising during system power-up
V
FB
rising during overvoltage event, I
PGOOD
= 1 mA
I
PGOOD
= 1 mA
PGOOD = 5 V
542
30
691
30
143
1
568
710
200
400
mV
mV
mV
mV
mV
nA
Rev. A | Page 4 of 44
Data Sheet
Parameter
TRACKING
Track Input Voltage Range
FB-to-Tracking Offset Voltage
Leakage Current
1
ADP1874/ADP1875
Symbol
Test Conditions/Comments
Min
0
0.5 V < TRACK < 0.6 V, offset = V
FB
− V
TRACK
V
TRACK
= 5 V
63
1
Typ
Max
5
50
Unit
V
mV
nA
The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 59 and Figure 60), C
GATE
= 4.3 nF, and the upper side and lower
side MOSFETs being Infineon BSC042N03MS G.
2
Guaranteed by design.
3
Not automatic test equipment (ATE) tested.
Rev. A | Page 5 of 44
