Changes to Specifications Section .................................................. 3
Change to Output Accuracy Voltage Parameter, Table 1 ............ 3
Changes to Ordering Guide .......................................................... 19
10/2016—Revision 0: Initial Version
Rev. B | Page 2 of 19
Data Sheet
SPECIFICATIONS
ADP7183
V
IN
= (V
OUT
− 0.5 V) or −2 V (whichever is more negative), EN = V
IN
, I
OUT
= −10 mA, C
IN
= C
OUT
= 4.7 µF, C
AFB
= 10 nF, C
A
= C
REG
= 1 µF, T
A
=
25°C for typical specifications, T
J
= −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.
Table 1.
Parameter
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT
SHUTDOWN CURRENT
OUTPUT NOISE
1
Symbol
V
IN
I
GND
I
GND-SD
OUT
NOISE
Test Conditions/Comments
I
OUT
= 0 µA
I
OUT
= −300 mA
EN = GND, V
IN
= −5.5 V
10 Hz to 100 kHz, C
AFB
= 1 nF
10 Hz to 100 kHz, C
AFB
= 10 nF
100 Hz to 100 kHz, C
AFB
= 1 nF
100 Hz to 100 kHz, C
AFB
= 10 nF
100 Hz, C
AFB
= 1 nF
100 Hz, C
AFB
= 10 nF
10 kHz to 1 MHz, C
AFB
= 1 nF to 1 µF
I
OUT
= −300 mA, V
OUT
= −3.3 V, V
IN
= −3.8 V
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
I
OUT
= −10 mA, T
A
= 25°C
−1 mA < I
OUT
< −300 mA,
V
IN
= (V
OUT
− 0.5 V) to −5.5 V
Adjustable model voltage reference
Adjustable model, V
IN
= −2 V, I
OUT
= −10 mA
V
IN
= (V
OUT
− 0.5 V) to −5.5 V
I
OUT
= −1 mA to −300 mA
−1 mA < I
OUT
< −300 mA,
V
IN
= (V
OUT
− 0.5 V) to −5.5 V
−1 mA < I
OUT
< −300 mA,
V
IN
= (V
OUT
− 0.5 V) to −5.5 V
I
OUT
= −100 mA
I
OUT
= −300 mA
V
EN
= 0 V
V
OUT
= −1 V
V
REG
= −1 V
V
A
= −1 V
V
OUT
= −4.5 V, C
AFB
= 1 nF, C
A
= 1 µF
V
OUT
= −4.5 V, C
AFB
= 10 nF, C
A
= 1 µF
V
OUT
= −1.2 V, C
AFB
= 1 nF, C
A
= 1 µF
V
OUT
= −1.2 V, C
AFB
= 10 nF, C
A
= 1 µF
V
OUT
= −0.5 V, no C
AFB
, C
A
= 1 µF
−400
T
J
rising
−0.5
−0.5
−2.6
−0.487
−2.6
−0.1
0.8
−10
−10
−40
−130
280
1.3
61
15
55
4
10
1.5
−600
150
15
−65
−220
−0.5
Min
−2.0
Typ
−0.6
−4.0
−2
7
5
6
4
300
100
20
85
75
62
40
−4.5
+0.5
+2.6
−0.513
+2.6
+0.3
2.6
Max
−5.5
−0.90
−7.0
−7
Unit
V
mA
mA
µA
µV rms
µV rms
µV rms
µV rms
nV/√Hz
nV/√Hz
nV/√Hz
dB
dB
dB
dB
V
%
%
V
%
%/V
%/A
nA
nA
mV
mV
Ω
kΩ
Ω
ms
ms
ms
ms
ms
mA
°C
°C
NOISE SPECTRAL DENSITY
1
OUT
NSD
POWER SUPPLY REJECTION RATIO
1
PSRR
OUTPUT VOLTAGE
Output Voltage Accuracy
V
OUT
OUTPUT VOLTAGE REFERENCE FEEDBACK
V
AFB
Accuracy
REGULATION
Line
Load
2
INPUT BIAS CURRENT
SENSE
V
AFB
DROPOUT VOLTAGE
3
PULL-DOWN RESISTANCE
Output Voltage
Regulated Input Supply Voltage
Low Noise Reference Voltage
START-UP TIME
4
V
AFB
ΔV
OUT
/∆V
IN
∆V
OUT
/∆I
OUT
SENSE
I-BIAS
V
AFB-BIAS
V
DROPOUT
V
OUT-PULL
V
REG-PULL
V
A-PULL
t
START-UP
CURRENT-LIMIT THRESHOLD
5
THERMAL SHUTDOWN
Threshold
Hysteresis
I
LIMIT
TS
SD
TS
SD-HYS
−800
Rev. B | Page 3 of 19
ADP7183
Parameter
UNDERVOLTAGE LOCKOUT THRESHOLDS
Input Voltage
Rising
Falling
Hysteresis
EN INPUT (NEGATIVE)
Logic High
Logic Low
Hysteresis
Leakage Current
EN INPUT (POSITIVE)
Logic High
Logic Low
Leakage Current
1
2
Data Sheet
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
UVLO
RISE
UVLO
FALL
UVLO
HYS
V
EN-NEG-HIGH
V
EN-NEG_LOW
EN
HYS-NEG
I
EN-LKG
V
EN-POS-HIGH
V
EN-POS-LOW
I
EN-LKG
−2 V ≤ V
IN
≤ −5.5 V
V
OUT
= off to on
V
OUT
= on to off
EN = V
IN
or GND
−2 V ≤ V
IN
≤ −5.5 V
V
OUT
= off to on
V
OUT
= on to off
V
EN
= 5 V, V
IN
= −5.5 V
−1.77
−1.58
90
−1.3
−1.16
−0.96
191
−0.25
0.96
0.89
4.0
V
V
mV
V
V
mV
µA
V
V
µA
−0.88
1.25
6.0
0.5
Guaranteed by characterization but not production tested.
Based on an endpoint calculation using −1
mA
and −300 mA loads.
3
Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. Dropout applies only for output
voltages below −2 V.
4
Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.
5
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current-limit threshold for a
−3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of −3.0 V, or −2.7 V.
INPUT AND OUTPUT CAPACITOR RECOMMENDED SPECIFICATIONS
Table 2.
Parameter
CAPACITANCE
Minimum C
IN
and C
OUT
Capacitance
1
Minimum C
A
and C
REG
Capacitance
2
Minimum C
AFB
Capacitance
3
Capacitor Equivalent Series Resistance (ESR)
1
Symbol
C
IN
, C
OUT
C
A
, C
REG
C
AFB
R
ESR
Test Conditions/Comments
T
A
= −40°C to +125°C
Min
3.3
0.7
0.7
Typ
4.7
1
10
Max
Unit
µF
µF
nF
Ω
0.1
The minimum input and output capacitance must be greater than 3.3 µF over the full range of operating conditions. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any LDO.
2
The minimum C
A
and C
REG
capacitance must be greater than 0.7 µF over the full range of operating conditions. X7R and X5R type capacitors are recommended; Y5V
and Z5U capacitors are not recommended for use with any LDO.
3
The minimum C
AFB
capacitance must be greater than 0.7 nF over the full range of operating conditions. X7R and X5R type capacitors are recommended; Y5V and Z5U
capacitors are not recommended for use with any LDO.
Rev. B | Page 4 of 19
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
VOUT to GND
EN to GND
VA to GND
VAFB to GND
VREG to GND
SENSE to GND
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
+0.3 V to −6 V
+0.3 V to −V
IN
+5.0 V to −6 V
+0.3 V to −6 V
+0.3 V to −6 V
+0.3 V to −2.16 V
+0.3 V to −6 V
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
ADP7183
temperature (T
J
) of the device is dependent on the ambient
temperature (T
A
), the power dissipation of the device (P
D
), and
the junction to ambient thermal resistance of the package (θ
JA
).
Use the following equation to calculate the junction temperature
(T
J
) from the ambient temperature (T
A
) and power dissipation (P
D
):
T
J
=
T
A
+ (P
D
×
θ
JA
)
The junction to ambient thermal resistance (θ
JA
) of the package
is based on modeling and calculation using a 4-layer board. The
junction to ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The θ
JA
value may vary, depending on
the PCB material, layout, and environmental conditions. The
specified θ
JA
values are based on a 4-layer, 4 in. × 3 in. circuit board.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 4. Thermal Resistance
Package Type
CP-8-27
1
1
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The
ADP7183
can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that T
J
is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated.
In applications with moderate power dissipation and low printed
circuit board (PCB) thermal resistance, the maximum ambient
temperature can exceed the maximum limit as long as the
junction temperature is within specification limits. The junction
θ
JA
68.8
θ
JC
10.0
Unit
°C/W
Thermal impedance simulated values are based on JEDEC 2S2P thermal test
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