Blackfin Embedded
Processor with Codec
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
PROCESSOR FEATURES
Up to 600 MHz high performance Blackfin processor
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Accepts a wide range of supply voltages for internal and I/O
operations. See operating conditions in the published
ADSP-BF52x processor data sheet.
Programmable on-chip voltage regulator (ADSP-BF523/
ADSP-BF525/ADSP-BF527processors only)
Embedded low power audio codec
289-ball (12 mm x 12 mm) CSP_BGA package
132K bytes of on-chip memory
External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories
Flexible booting options from external flash, SPI and TWI
memory or from host devices including SPI, TWI, and UART
Code security with Lockbox Secure Technology
one-time-programmable (OTP) memory
Memory management unit providing memory protection
2 dual-channel memory DMA controllers
EMBEDDED CODEC FEATURES
Stereo, 24-bit ADCs and DACs
DAC SNR: 100 dB (A-weighted), THD: –80 dB at 48 kHz, 3.3 V
ADC SNR: 90 dB (A-weighted), THD: –80 dB at 48 kHz, 3.3 V
Highly efficient headphone amplifier
Stereo line input and monaural microphone input
Low power
7 mW stereo playback (1.8 V supply)
14 mW record and playback (1.8 V supply)
Low supply voltages
Analog: 1.8 V to 3.6 V
Digital core: 1.8 V min
Digital I/O: 1.8 V to 3.6 V
256 × f
S
/384 × f
S
oversampling rate in normal mode;
250 × f
S
/272 × f
S
oversampling rate in USB mode
Audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,
22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz,
and 96 kHz
PERIPHERALS
See the published ADSP-BF52x processor data sheet for
additional peripherals
WATCHDOG TIMER
OTP MEMORY
RTC
VOLTAGE REGULATOR*
JTAG TEST AND EMULATION
PERIPHERAL
COUNTER
SPORT0
ACCESS BUS
B
L1 INSTRUCTION
MEMORY
EAB
USB
16
L1 DATA
MEMORY
SPORT1
INTERRUPT
CONTROLLER
UART1
UART0
NFC
DMA
CONTROLLER
DCB
DEB
DMA
ACCESS
BUS
PPI
SPI
TIMER7-1
TIMER0
GPIO
PORT H
GPIO
PORT G
CODEC
GPIO
PORT F
EXTERNAL PORT
FLASH, SDRAM CONTROL
BOOT
ROM
EMAC
HOST DMA
TWI
PORT J
*REGULATOR AVAILABLE ON ADSP-BF523/ADSP-BF525/ADSP-BF527 PROCESSORS ONLY
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2010 Analog Devices, Inc. All rights reserved.
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
TABLE OF CONTENTS
Processor Features ................................................... 1
Embedded Codec Features ......................................... 1
Peripherals ............................................................. 1
Table of Contents ..................................................... 2
Revision History ...................................................... 2
General Description ................................................. 3
Codec Description ................................................ 3
ADC and DAC ..................................................... 4
ADC High-Pass and DAC De-Emphasis Filters ............ 4
Analog Audio Interfaces ......................................... 4
Stereo Line and Monaural Microphone Inputs .......... 4
Bypass and Sidetone Paths to Output ...................... 5
Line and Headphone Outputs ............................... 5
Digital Audio Interface ........................................... 6
Recording Mode ................................................ 8
Playback Mode .................................................. 8
Digital Audio Data Sampling Rate .......................... 8
Software Control Interface .................................... 11
Codec Pin Descriptions ........................................... 12
Register Details ..................................................... 15
Bit Descriptions .................................................. 16
Specifications ........................................................ 21
Operating Conditions ........................................... 21
Codec Electrical Characteristics .............................. 21
Absolute Maximum Ratings ................................... 23
ESD Sensitivity ................................................... 23
Package Information ............................................ 23
Power Consumption ............................................ 24
Timing Specifications ........................................... 25
TWI Timing ................................................... 25
SPI Timing ..................................................... 26
Digital Audio Interface Slave Mode Timing ............ 27
Digital Audio Interface Master Mode Timing .......... 28
System Clock Timing ........................................ 29
Digital Filter Characteristics ................................ 30
Converter Filter Response ..................................... 30
Digital De-Emphasis ............................................ 31
289-Ball CSP_BGA Ball Assignment ........................ 32
Outline Dimensions ................................................ 35
Ordering Guide ..................................................... 36
REVISION HISTORY
3/10—Rev. 0 to Rev. A
Revised the following figures.
Recommended Application Circuit Using SPI Control .... 13
Recommended Application Circuit Using TWI Control .. 14
Added Sampling Rate = 48 kHz to all figures in
Converter Filter Response ........................................ 30
Revised
Ordering Guide .......................................... 36
Rev. A
| Page 2 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
GENERAL DESCRIPTION
This document describes the differences between the
ADSP-BF52xC and the ADSP-BF52x standard Blackfin
®
prod-
uct. Please refer to the published ADSP-BF52x data sheet for
general description and specifications. This document only
describes the differences from that data sheet.
The ADSP-BF52xC processors add a low power, high quality
stereo audio codec for portable digital audio applications with
one set of stereo programmable gain amplifier (PGA) line
inputs and one monaural microphone input. It features two 24-
bit analog-to-digital converter (ADC) channels and two 24-bit
digital-to-analog (DAC) converter channels.
The codec can operate as a master or a slave. It supports various
master clock frequencies, including 12 MHz or 24 MHz for USB
devices; standard 256 × f
S
or 384 × f
S
based rates, such as
12.288 MHz and 24.576 MHz; and many common audio sam-
pling rates, such as 96 kHz, 88.2 kHz, 48 kHz, 44.1 kHz, 32 kHz,
24 kHz, 22.05 kHz, 16 kHz, 12 kHz, 11.025 kHz, and 8 kHz.
The codec can operate at power supplies as low as 1.8 V for the
analog circuitry and as low as 1.8 V for the digital circuitry. The
maximum voltage supply is 3.6 V for all supplies.
CSB
AVDD
CONTROL INTERFACE
HPVDD
VMID
CODEC
HPGND
CSDA
The codec software-programmable stereo output options
provide the programmer with many application possibilities
because the device can be used as a headphone driver or as a
speaker driver. Its volume control functions provide a large
range of gain control of the audio signal.
CODEC DESCRIPTION
The ADSP-BF52xC codec contains a central clock source, called
the codec master clock (CODEC_MCLK) that produces a refer-
ence clock for all internal audio data processing and synch-
ronization. When using an external clock source to drive the
CODEC_MCLK pin, care should be taken to select a clock
source with less than 50 ps of jitter. Without careful generation
of the CODEC_MCLK signal, the digital audio quality
will suffer.
To enable the codec to generate the central reference clock
in a system, connect a crystal oscillator between the XTI/
CODEC_MCLK input pin and the XTO output pin.
CSCL CMODE
AGND
MUTE
ATTEN/
MUTE
MICBIAS
RLINEIN
VOLUME
MUTE
MUTE
MIC
BOOST
MUTE
LLINEIN
VOLUME
MUTE
MUX
ADC
DAC
MUTE
Σ
ROUT
MICIN
DIGITAL
FILTERS
LOUT
MUX
ADC
DAC
MUTE
Σ
VOLUME/
MUTE
ATTEN/
MUTE
OSCPD
OSC
CLKIN
DIVIDER
XTI/CODEC_MCLK
CLKOUT
DIVIDER
CODEC_CLKOUT
DACDAT
DIGITAL AUDIO INTERFACE
ADCLRC
MUTE
HEADPHONE
LHPOUT
DRIVER
VOLUME/
MUTE
HEADPHONE
RHPOUT
DRIVER
DACLRC
XTO
Figure 1. Codec Block Diagram
Rev. A
| Page 3 of 36 | March 2010
CODEC_BCLK
ADCDAT
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
To allow an external device to generate the central reference
clock, apply the external clock signal directly through the XTI/
CODEC_MCLK input pin. In this configuration, the oscillator
circuit of the codec can be powered down by using the OSCPD
bit (Register R6, Bit D5) to reduce power consumption.
To accommodate applications with very high frequency master
clocks, the internal core reference clock of the codec can be set
to either CODEC_MCLK or CODEC_MCLK divided by 2. This
is enabled by adjusting the setting of the CLKDIV2 bit (Register
R8, Bit D6). The CODEC_CLKOUT pin can also drive external
clock sources with either the codec clock signal or codec clock
divided by 2 by enabling the CLKODIV2 bit (Register R8,
Bit D7).
ANALOG AUDIO INTERFACES
The codec includes stereo single-ended line inputs and a mon-
aural microphone input to the on-board ADC. Either the line
inputs or the microphone input, but not both simultaneously,
can be connected to the ADC by setting the INSEL bit (Register
R4, Bit D2).
The codec also includes line and headphone outputs from the
on-board DAC. The line or microphone inputs can be routed
and mixed directly to the output terminals.
Stereo Line and Monaural Microphone Inputs
The single-ended stereo line inputs (RLINEIN and LLINEIN)
are internally biased to VMID by way of a voltage divider
between AVDD and AGND (see
Figure 2).
The line input signal
can be connected to the internal ADC and, if desired, routed
directly to the outputs via the bypass path by using the BYPASS
bit (Register R4, Bit D3).
RLINEIN
or
LLINEIN
AVDD
ADC AND DAC
The codec contains a pair of oversampling
Σ-Δ
ADCs. The
maximum ADC full-scale input level is 1.0 V
rms
when
AVDD = 3.3 V. If the input signal to the ADC exceeds this
level, data overloading occurs and causes audible distortion.
The ADC can accept analog audio input from either the stereo
line inputs or the monaural microphone input. Note that the
ADC can only accept input from a single source, so the pro-
grammer must choose either the line inputs or the microphone
input using the INSEL bit (Register R4, Bit D2). The digital data
from the ADC output, once converted, is processed using the
ADC filters.
Complementary to the
Σ-Δ
ADC channels, the codec contains a
pair of oversampling DACs that convert the digital audio data
from the internal DAC filters into an analog audio signal. The
DAC output can also be muted by setting the DACMU bit (Reg-
ister R5, Bit D3) in the control register.
–
VMID
+
ADC
OR
BYPASS
INTERNAL CIRCUITRY
AGND
Figure 2. Line Input to ADC
ADC HIGH-PASS AND DAC DE-EMPHASIS FILTERS
The ADC and DAC employ separate digital filters that perform
24-bit signal processing. The digital filters are used for both
record and playback modes and are optimized for each individ-
ual sampling rate used.
For recording mode operations, the unprocessed data from the
ADC enters the ADC filters and is converted to the appropriate
sampling frequency, then is output to the digital audio interface.
For playback mode operations, the DAC filters convert the digi-
tal audio interface data to oversampled data using a sampling
rate selected by the programmer. The oversampled data is pro-
cessed by the DAC and sent to the analog output mixer by
enabling the DACSEL (Register R4, Bit D4).
Programmers have the option of setting up the device so that
any dc offset in the input source signal is automatically detected
and removed. To accomplish this, enable the digital high-pass
filter (see
Table 22 on Page 30
for characteristics) contained in
the ADC digital filters by using the ADCHPD bit (Register R5,
Bit D0).
In addition, programmers can implement digital de-emphasis
by using the DEEMPH bits (Register R5, Bit D1 and Bit D2).
The line input volume can be adjusted from –34.5 dB to +33 dB
in steps of +1.5 dB by setting the LINVOL (Register R0, Bit D0
to Bit D5) and RINVOL (Register R1, Bit D0 to Bit D5) bits. By
default the volume is independently adjustable for both right
and left line inputs. However, if the LRINBOTH or RLINBOTH
bit is programmed, both LINVOL and RINVOL are loaded with
the same value. The programmer can also set the LINMUTE
(Register R0, Bit D7) and RINMUTE (Register R1, Bit D7) bits
to mute the line input signal to the ADC.
The high impedance, low capacitance monaural microphone
input pin (MICIN, shown in
Figure 3
) has two gain stages and a
microphone bias level (MICBIAS) that is internally biased to the
VMID voltage level by way of a voltage divider between AVDD
and AGND. The microphone input signal can be connected to
the internal ADC and, if desired, routed directly to the outputs
via the sidetone path by using the SIDETONE bit (Register R4,
Bit D5).
Rev. A
| Page 4 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
50kΩ
R
EXT
MICIN
10kΩ
selected level of attenuation occurs after the initial microphone
signal amplification from the microphone first and second stage
gains.
0dB/20dB/40dB
GAIN BOOST
Line and Headphone Outputs
The DAC outputs, the microphone (the sidetone path), and the
line inputs (the bypass path) are summed at an output mixer
(see
Figure 4).
This output signal is then applied to both the ste-
reo line outputs and stereo headphone outputs.
AVDD
VMID
ADC
OR
SIDETONE
BYPASS
AGND
INTERNAL CIRCUITRY
LINE
INPUT
Figure 3. Microphone Input to ADC
SIDETONE
MICROPHONE
INPUT
The first gain stage is composed of a low noise operational
amplifier set to an inverting configuration with integrated
50 kΩ feedback and 10 kΩ input resistors. The default micro-
phone input signal gain is 14 dB. An external resistor (R
EXT
) can
be connected in series with the MICIN pin to reduce the first-
stage gain of the microphone input signal to as low as 0 dB by
using the following equation:
Microphone Input Gain = 50 kΩ/(10 kΩ + R
EXT
)
The second-stage gain of the microphone signal path is derived
from the internal microphone boost circuitry. The available set-
tings are 0 dB, 20 dB, and 40 dB and are controlled by the
MICBOOST (Register R4, Bit D0) and MICBOOST2 (Register
R4, Bit D8) bits. To achieve 20 dB of secondary gain boost, the
programmer can select either MICBOOST or MICBOOST2. To
achieve 40 dB of secondary microphone signal gain, the pro-
grammer must select both MICBOOST and MICBOOST2.
The MUTEMIC bit (Register R4, Bit D1) mutes the microphone
input signal to the ADC.
When using either the line or microphone inputs, the maximum
full-scale input to the ADC is 1.0 V rms when AVDD = 3.3 V.
Do not apply an input voltage larger than full-scale to avoid
overloading the ADC, which causes distortion of sound and
deterioration of audio quality. For best sound quality in both
microphone and line inputs, gain should be carefully configured
so that the ADC receives a signal equal to its full-scale. This
maximizes the signal-to-noise ratio for best total audio quality.
DACSEL
DAC
OUTPUT
LINE OUTPUT
AND
HEADPHONE
OUTPUT
AVDD
VMID
AGND
INTERNAL CIRCUITRY
Figure 4. Output Signal Chain
The codec has a set of efficient headphone amplifier outputs,
LHPOUT and RHPOUT, that are able to drive 16
Ω
or 32
Ω
headphones (shown in
Figure 5).
DAC/
SIDETONE/
BYPASS
AVDD
–
VMID
+
RHPOUT
or
LHPOUT
Bypass and Sidetone Paths to Output
The line and microphone inputs can be routed and mixed
directly to the output terminals by programming the SIDET-
ONE (Register R4, Bit D5) and BYPASS (Register R4, Bit D3)
registers. In both modes, the analog input signal is routed
directly to the output terminals and is not digitally converted.
The bypass signal at the output mixer is the same level as the
output of the PGA associated with each line input.
The sidetone signal at the output mixer can be attenuated from
–6 dB to –15 dB in steps of –3 dB by configuring the SIDEATT
(Register R4, Bit D6 and Bit D7) control register bits. The
INTERNAL CIRCUITRY
AGND
Figure 5. Headphone Output
Like the line inputs, the LHPOUT and RHPOUT volumes, by
default, are independently adjusted by setting the LHPVOL
(Register R2, Bit D0 to Bit D6) and RHPVOL (Register R3, Bit
D0 to Bit D6) bits of the headphone output control registers.
The headphone outputs can be muted by writing codes less than
0110000 to the LHPVOL and RHPVOL bits.
Rev. A
| Page 5 of 36 | March 2010
