a
High End, Multichannel,
32-Bit Floating-Point Audio Processor
SST-Melody -SHARC
®
®
FUNCTIONAL BLOCK DIAGRAM
SDRAM
128K 32,
BOOT ROM
1M 8
IRQ
GPIO
FEATURES
Super Harvard Architecture Computer (SHARC)
4 Independent Buses for Dual Data, Instruction, and
I/O Fetch on a Single Cycle
32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-
Point Arithmetic
544 Kbits On-Chip SRAM Memory, Integrated I/O
Peripheral I
2
S Support for 8 Simultaneous Receive and
Transmit Channels
66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained
Performance
User-Configurable 544 Kbits On-Chip SRAM Memory
2 External Port, DMA Channels and 8 Serial Port,
DMA Channels
Decodes Industry Standard Formats Using a 32-Bit
Floating Point Implementation for Decoding
Dolby
®
Digital AC-3, Dolby Digital EX Processing
Dolby Pro Logic
®
, 96 kHz, Dolby Pro Logic II
Dolby Headphone, Dolby 3/0
DTS
®
5.1, DTS-ES
®
-Discreet 6.1, DTS Matrix and Matrix 3.0,
DTS 96/24
®
, DTS NEO:6
THX
®
Ultra, Select, Ultra2, 5.1, 7.1, EX
SRS
®
Labs Circle Surround II
TM
, Virtual Loudspeaker
MPEG AAC, MPEG2 Decode, MPEG 2-Channel Decode
PCM, PCM 96 kHz
HDCD, MLP*
Delay 7.1, 96 kHz
Bass 7.1, 96 kHz, Bass/Treble 2 Channel
ADI Surround: Club, Music, and Stadium
AAC (LC), AAC (LC) 2 Channel, AAC MP
WaveSurround 5.1 Channel to Headphone, Stereo to
Headphone, Channel to Loudspeaker, Stereo to
Loudspeaker
Downsampling 96 kHz to 48 kHz (2-Channel)
3-Band Equalizer, 2-Channel
Encoders: AC-3 2-Channel Consumer Encoder
Single Chip DSP-Based Implementation of Digital Audio
Algorithms
2
I S Compatible Ports
Interface to External SDRAM
SST-Melody-SHARC
ADC
SERIAL PORT
DAC
ALGORITHMS
COMMAND
S/PDIF
TRANSMITTER
KERNEL
S/PDIF
RECEIVER
DMA CONNECTION
OR DUAL BUFFER
HOST MICRO
Easy Interfaces to Audio Codecs
96 kHz Processing
Supports Customer Specific Post Processing
Automatic Stream Detection and Code Loading
Easy to Use Software Architecture
Optimized Library of Routines
Host Communication Using 16-Bit Parallel Port or SPI Port
Highly Flexible Serial Ports
SRAM Interface for More Delay
Supports IEC60958 For Bit Streams
8-Channel Output Using TDM Codecs
APPLICATIONS
Home Theater AVR Systems
Automotive Audio Receivers
Video Game Consoles
DVD Players
Cable and Satellite Set-Top Boxes
Multimedia Audio/Video Gateways
GENERAL DESCRIPTION
Melody and SHARC are registered trademarks of Analog Devices, Inc.
DTS, DTS-ES, and DTS 96/24 are registered trademarks of Digital Theater
Systems, Inc.
Dolby and Pro Logic are registered trademarks of Dolby Laboratories
Licensing Corporation.
SRS is a registered trademark and Circle Surround II is a trademark of SRS Labs.
THX is a registered trademark of the THX, Ltd.
*MLP
is implemented, not certified.
The SST-Melody-SHARC family of powerful 32-bit Audio Proces-
sors from Analog Devices provides flexible solutions and delivers
a host of features across high end and high fidelity audio systems
to the AV receiver and DVD markets. It includes multichannel
audio decoders, encoders, and post processors for digital
audio designs using DSP chipsets in home theater systems and
automotive audio receivers.
(continued on page 11)
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
SST-Melody-SHARC–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
1
Parameter
V
DD
T
CASE
V
IH
V
IL1
V
IL2
Test
Conditions
Supply Voltage
Case Operating Temperature
High Level Input Voltage
@ V
DD
= max
2
Low Level Input Voltage
@ V
DD
= min
3
Low Level Input Voltage
@ V
DD
= min
C Grade
Min
Max
3.13
–40
2.0
–0.5
–0.5
3.60
+100
V
DD
+ 0.5
+0.8
+0.7
K Grade
Min
Max
3.13
0
2.0
–0.5
–0.5
3.60
+85
V
DD
+ 0.5
+0.8
+0.7
Unit
V
°C
V
V
V
NOTES
1
See Environmental Conditions section for information on thermal specifications.
2
Applies to input and bidirectional pins: DATA31–0, ADDR23–0, BSEL,
RD, WR, SW,
ACK,
SBTS, IRQ2–0,
FLAG11–0,
HBG, CS, DMAR1, DMAR2, BR2–1, ID2–0,
RPBA,
CPA,
TFS0, TFS1, RFS0, RFS1,
BMS,
TMS, TDI, TCK,
HBR,
DR0A, DR1A, DR0B, DR1B, TCLK0, TCLK1, RCLK0, RCLK1,
RESET, TRST,
PWM_EVENT0, PWM_EVENT1,
RAS, CAS, SDWE, SDCKE.
3
Applies to input pin CLKIN.
ELECTRICAL CHARACTERISTICS
Parameter
V
OH
V
OL
I
IH
I
IL
I
ILP
I
OZH
I
OZL
I
OZLS
I
OZLA
I
OZLAR
I
OZLC
C
IN
High Level Output Voltage
Low Level Output Voltage
1
High Level Input Current
3
Low Level Input Current
3
Low Level Input Current
4
Three-State Leakage Current
5, 6, 7, 8
Three-State Leakage Current
5
Three-State Leakage Current
6
Three-State Leakage Current
9
Three-State Leakage Current
8
Three-State Leakage Current
7
Input Capacitance
10, 11
1
Test Conditions
@ V
DD
= min, I
OH
= –2.0 mA
@ V
DD
= min, I
OL
= +4.0 mA
2
@ V
DD
= max, V
IN
= V
DD
max
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= V
DD
max
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= 1.5 V
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= 0 V
f
IN
= 1 MHz, T
CASE
= 25°C, V
IN
= 2.5 V
2
C and K Grades
Min
Max
2.4
0.4
10
10
150
10
8
150
350
4
1.5
8
Unit
V
V
µA
µA
µA
µA
µA
µA
µA
mA
mA
pF
NOTES
1
Applies to output and bidirectional pins: DATA31–0, ADDR 23–0,
MS3–0, RD, WR, SW,
ACK, FLAG11–0,
HBG,
REDY,
DMAG1, DMAG2, BR2–1, CPA,
TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, DT0A, DT1A, DT0B, DT1B, XTAL,
BMS,
TDO,
EMU,
BMSTR, PWM_EVENT0,
PWM_EVENT1,
RAS, CAS,
DQM,
SDWE,
SDCLK0, SDCLK1,
SDCKE,
SDA10.
2
See Output Drive Current section for typical drive current capabilities.
3
Applies to input pins: ACK,
SBTS,
IRQ2–0,
HBR, CS, DMAR1, DMAR2,
ID1–0, BSEL, CLKIN,
RESET,
TCK (Note that ACK is pulled up internally with 2 kΩ
during reset in a multiprocessor system, when ID1–0 = 01 and another SST-Melody-SHARC is not requesting bus mastership).
4
Applies to input pins with internal pull-ups: DR0A, DR1A, DR0B, DR1B,
TRST,
TMS, TDI.
5
Applies to three-statable pins: DATA31–0, ADDR 23–0,
MS3–0, RD, WR, SW,
ACK, FLAG11–0, REDY,
HBG, DMAG1, DMAG2, BMS,
TDO,
RAS, CAS,
DQM,
SDWE,
SDCLK0, SDCLK1,
SDCKE,
SDA10, and
EMU
(note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system,
when ID1–0 = 01 and another SST-Melody-SHARC is not requesting bus mastership).
6
Applies to three-statable pins with internal pull-ups: DT0A, DT1A, DT0B, DT1B, TCLK0, TCLK1, RCLK0, RCLK1.
7
Applies to
CPA
pin.
8
Applies to ACK pin when pulled up.
9
Applies to ACK pin when keeper latch enabled.
10
Guaranteed but not tested.
11
Applies to all signal pins.
Specifications subject to change without notice.
–2–
REV. 0
SST-Melody-SHARC
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
DD
+ 0.5 V
Output Voltage Swing . . . . . . . . . . . . . . –0.5 V to V
DD
+ 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . . 130°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . . . . 280°C
*Stresses
greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only; functional opera-
tion of the device at these or any other conditions greater than those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Part Number
ADSST-21065LKS-240
ADSST-21065LCS-240
ADSST-21065LKCA-240
ADSST-21065LKS-264
ADSST-21065LKCA-264
Case Temperature
Range
0°C to 85°C
–40°C to +100°C
0°C to 85°C
0°C to 85°C
0°C to 85°C
Instruction
Rate (MHz)
60
60
60
66
66
On-Chip
SRAM (Kbit)
544
544
544
544
544
Operating
Voltage (V)
3.3
3.3
3.3
3.3
3.3
Package
Options
S-208-2
S-208-2
BC-196
S-208-2
BC-196
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
SST-Melody-SHARC features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. 0
–3–
SST-Melody-SHARC
208-LEAD MQFP PIN CONFIGURATIONS
167
GND
166
ADDR18
165
ADDR19
164
ADDR20
162
ADDR21
161
ADDR22
160
ADDR23
180
ADDR9
179
ADDR10
178
ADDR11
175
ADDR12
174
ADDR13
173
ADDR14
172
VDD
171
ADDR15
170
ADDR16
169
ADDR17
195
ADDR0
194
ADDR1
193
ADDR2
192
VDD
191
VDD
190
ADDR3
189
ADDR4
188
ADDR5
185
ADDR6
184
ADDR7
183
ADDR8
182
VDD
VDD
RSF0
GND
RCLK0
DR0A
DR0B
TFS0
TCLK0
VDD
GND
DT0A
DT0B
RFS1
GND
RCLK1
DR1A
DR1B
TFS1
TCLK1
VDD
VDD
DT1A
DT1B
PWM EVENT1
GND
PWM EVENT0
BR1
BR2
VDD
CLKIN
XTAL
VDD
GND
SDCLK1
GND
VDD
SDCLK0
DMAR1
DMAR2
HBR
GND
RAS
CAS
SDWE
VDD
DQM
SDCKE
SDA10
GND
DMAG1
DMAG2
HBG
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
PIN 1
IDENTIFIER
157
RESET
202
NC
201
FLAG3
199
FLAG2
198
FLAG1
197
FLAG0
196
GND
208
NC
207
IRQ2
206
IRQ1
205
IRQ0
159
GND
158
VDD
204
GND
203
NC
187
GND
186
GND
181
GND
177
GND
168
GND
163
VDD
200
VDD
176
VDD
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
OO
ADSST-21065L
TOP VIEW
(Not to Scale)
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VDD
GND
GND
BMS
BSEL
TCK
GND
TMS
TDI
TRST
TDO
EMU
ID0
ID1
NC
VDD
VDD
GND
FLAG4
FLAG5
FLAG6
GND
FLAG7
DATA31
DATA30
VDD
VDD
GND
DATA29
DATA28
DATA27
GND
VDD
DATA26
DATA25
DATA24
VDD
GND
DATA23
DATA22
DATA21
NC
GND
DATA20
DATA19
DATA18
VDD
DATA17
DATA16
DATA15
GND
VDD
100
101
102
BMSTR
VDD
CS
SBTS
GND
WR
RD
GND
VDD
GND
REDY
SW
CPA
VDD
VDD
GND
ACK
MS0
MS1
GND
GND
MS2
MS3
FLAG11
VDD
FLAG10
FLAG9
FLAG8
GND
DATA0
DATA1
DATA2
VDD
DATA3
DATA4
DATA5
GND
DATA6
DATA7
DATA8
VDD
GND
VDD
DATA9
DATA10
DATA11
GND
DATA12
DATA13
NC
NC
DATA14
NC = NO CONNECT
–4–
103
104
92
93
94
95
96
97
98
73
74
75
76
77
78
79
80
81
83
84
85
86
87
88
89
90
53
54
55
56
57
58
59
60
61
70
71
72
62
63
64
65
66
67
68
69
82
91
99
REV. 0
SST-Melody-SHARC
196-BALL
CSPBGA
PIN CONFIGURATION
14
NC7
13
NC8
12
ADDR18
11
ADDR17
10
ADDR14
9
ADDR11
8
ADDR8
7
ADDR7
6
ADDR6
5
ADDR3
4
ADDR0
3
FLAG2
2
NC2
1
NC1
A
TCK
GND
ADDR23
ADDR21
ADDR19
ADDR15
ADDR12
ADDR9
ADDR5
ADDR2
FLAG0
IRQ0
RFS0
DR0A
B
TDO
BSEL
RESET
ADDR22
ADDR20
ADDR16
ADDR13
ADDR10
ADDR4
ADDR1
FLAG3
IRQ2
RCLK0
TCLK0
C
EMU
TRST
TMS
BMS
VDD
VDD
VDD
VDD
VDD
FLAG1
IRQ1
DR0B
TFS0
RCLK1
D
FLAG4
ID1
TDI
ID0
VDD
GND
GND
GND
GND
VDD
RFS1
DT0A
DT0B
TFS1
E
FLAG7
FLAG5
FLAG6
VDD
GND
GND
GND
GND
GND
GND
VDD
DR1A
DR1B
TCLK1
F
DATA29
DATA30
DATA31
VDD
GND
GND
GND
GND
GND
GND
VDD
DT1A
DT1B
PWM_
EVENT1
PWM_
EVENT0
G
DATA26
DATA27
DATA28
VDD
GND
GND
GND
GND
GND
GND
VDD
BR2
BR1
H
DATA23
DATA25
DATA24
VDD
GND
GND
GND
GND
GND
GND
VDD
SDCLK1
XTAL
CLKIN
J
DATA22
DATA20
DATA21
DATA19
VDD
GND
GND
GND
GND
VDD
SDWE
HBR
SDCLK0
DMAR1
K
DATA18
DATA17
DATA16
DATA13
DATA8
VDD
VDD
VDD
VDD
VDD
DMAG2
SDA10
CAS
DMAR2
L
DATA15
DATA14
DATA12
DATA9
DATA5
DATA2
FLAG10
ACK
CPA
RD
CS
DMAG1
SDCKE
RAS
M
NC6
DATA11
DATA10
DATA7
DATA4
DATA1
FLAG11
MS1
GND
REDY
SBTS
BMSTR
HBG
DQM
N
NC5
DATA6
DATA3
DATA0
FLAG8
FLAG9
MS3
MS2
MS0
SW
WR
GND
NC4
NC3
P
REV. 0
–5–
嵌入式系统
