Change to Features Section ............................................................. 1
Changes to Regulatory Information Section and Table 5 ........... 9
7/2015—Revision 0: Initial Version
Rev. A | Page 2 of 17
Enhanced Product
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
ADuM3400-EP/ADuM3401-EP/ADuM3402-EP
All voltages are relative to their respective ground. 4.5 V ≤ V
DD1
≤ 5.5 V and 4.5 V ≤ V
DD2
≤ 5.5 V. All minimum/maximum specifications
apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 5 V.
Table 1.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM3400-EP,
Total Supply Current
1
DC to 2 Mbps
V
DD1
Supply Current
V
DD2
Supply Current
10 Mbps
V
DD1
Supply Current
V
DD2
Supply Current
ADuM3401-EP,
Total Supply Current
1
DC to 2 Mbps
V
DD1
Supply Current
V
DD2
Supply Current
10 Mbps
V
DD1
Supply Current
V
DD2
Supply Current
ADuM3402-EP,
Total Supply Current
1
DC to 2 Mbps
V
DD1
or V
DD2
Supply Current
10 Mbps
V
DD1
or V
DD2
Supply Current
For All Models
Input Leakage per Channel
V
Ex
Input Pull-Up Current
Tristate Leakage Current per Channel
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Symbol
I
DDI (Q)
I
DDO (Q)
Min
Typ
0.57
0.29
Max Unit
0.83 mA
0.35 mA
Test Conditions/Comments
I
DD1 (Q)
I
DD2 (Q)
I
DD1 (10)
I
DD2 (10)
2.9
1.2
9.0
3.0
3.5
1.9
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
5 MHz logic signal frequency
5 MHz logic signal frequency
11.6 mA
5.5 mA
I
DD1 (Q)
I
DD2 (Q)
I
DD1 (10)
I
DD2 (10)
2.5
1.6
7.4
4.4
3.2
2.4
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
5 MHz logic signal frequency
5 MHz logic signal frequency
10.6 mA
6.5 mA
I
DD1 (Q)
, I
DD2 (Q)
I
DD1 (10)
, I
DD2 (10)
I
I
I
PU
I
OZ
V
IH
, V
EH
V
IL
, V
EL
V
OAH
, V
OBH
V
OCH
, V
ODH
−10
−10
−10
2.0
(V
DD1
or V
DD2
) −
0.1
(V
DD1
or V
DD2
) −
0.4
2.0
6.0
2.8
7.5
mA
mA
DC to 1 MHz logic signal frequency
5 MHz logic signal frequency
0 V ≤ V
Ix
≤ V
DDx
V
Ex
= 0 V
+0.01 +10 µA
−3
+0.01 +10 µA
V
0.8 V
5.0
V
4.8
0.0
0.04
0.2
0.1
0.1
0.4
100
V
V
V
V
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
I
Ox2
= −20 µA, V
Ix
= V
IxH3
I
Ox2
= −4 mA, V
Ix
= V
IxH3
I
Ox2
= 20 µA, V
Ix
= V
IxL4
I
Ox2
= 400 µA, V
Ix
= V
IxL4
I
Ox2
= 4 mA, V
Ix
= V
IxL4
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
Logic Low Output Voltages
V
OAL
, V
OBL
V
OCL
, V
ODL
SWITCHING SPECIFICATIONS
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
PLH
− t
PHL
|
Change vs. Temperature
Propagation Delay Skew
Channel to Channel Matching
Codirectional Channels
Opposing Directional Channels
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
t
PSKOD
10
20
32
5
50
3
15
3
6
Rev. A | Page 3 of 17
ADuM3400-EP/ADuM3401-EP/ADuM3402-EP
Parameter
For All Models
Output Propagation Delay
Disable (High/Low to High Impedance)
Enable (High Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
Logic High Output
5
Logic Low Output
5
Refresh Rate
Dynamic Supply Current per Channel
6
Input
Output
1
Enhanced Product
Typ
Max Unit
Test Conditions/Comments
Symbol
Min
t
PHZ
, t
PLH
t
PZH
, t
PZL
t
R
/t
F
|CM
H
|
|CM
L
|
f
r
I
DDI (D)
I
DDO (D)
25
25
6
6
2.5
35
35
1.2
0.20
0.05
8
8
ns
ns
ns
kV/µs
kV/µs
Mbps
mA/Mbps
mA/Mbps
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
V
Ix
= V
DD1
/V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11
through Figure 15 for total V
DD1
and V
DD2
supply currents as a function of data rate for
ADuM3400-EP/ADuM3401-EP/ADuM3402-EP
channel configurations.
2
I
Ox
is the Channel x output current, where x = A, B, C, or D.
3
V
IxH
is the input side logic high.
4
V
IxL
is the input side logic low.
5
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining the output voltage (V
OUT
) > 0.8 V
DD2
. CM
L
is the maximum common-
mode voltage slew rate that can be sustained while maintaining V
OUT
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges. The transient magnitude is the range over which the common mode is slewed.
6
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions.
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All voltages are relative to their respective ground. 3.135 V ≤ V
DD1
≤ 3.6 V and 3.135 V ≤ V
DD2
≤ 3.6 V. All minimum/maximum specifications
apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 3.3 V.
Table 2.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM3400-EP,
Total Supply Current
1
DC to 2 Mbps
V
DD1
Supply Current
V
DD2
Supply Current
10 Mbps
V
DD1
Supply Current
V
DD2
Supply Current
ADuM3401-EP,
Total Supply Current
1
DC to 2 Mbps
V
DD1
Supply Current
V
DD2
Supply Current
10 Mbps
V
DD1
Supply Current
V
DD2
Supply Current
ADuM3402-EP,
Total Supply Current
1
DC to 2 Mbps
V
DD1
or V
DD2
Supply Current
10 Mbps
V
DD1
or V
DD2
Supply Current
Symbol
I
DDI (Q)
I
DDO (Q)
Min
Typ
0.31
0.19
Max Unit
0.49 mA
0.27 mA
Test Conditions/Comments
I
DD1 (Q)
I
DD2 (Q)
I
DD1 (10)
I
DD2 (10)
1.6
0.7
4.8
1.8
2.1
1.2
7.1
2.3
mA
mA
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
5 MHz logic signal frequency
5 MHz logic signal frequency
I
DD1 (Q)
I
DD2 (Q)
I
DD1 (10)
I
DD2 (10)
1.4
0.9
4.1
2.5
1.9
1.5
5.6
3.3
mA
mA
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
5 MHz logic signal frequency
5 MHz logic signal frequency
I
DD1 (Q)
, I
DD2 (Q)
I
DD1 (10)
, I
DD2 (10)
1.2
3.3
1.7
4.4
mA
mA
DC to 1 MHz logic signal frequency
5 MHz logic signal frequency
Rev. A | Page 4 of 17
Enhanced Product
Parameter
For All Models
Input Leakage per Channel
V
Ex
Input Pull-Up Current
Tristate Leakage Current per Channel
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Symbol
I
I
I
PU
I
OZ
V
IH
, V
EH
V
IL
, V
EL
V
OAH
, V
OBH
V
OCH
, V
ODH
Logic Low Output Voltages
V
OAL
, V
OBL
V
OCL
, V
ODL
Min
−10
−10
−10
1.6
ADuM3400-EP/ADuM3401-EP/ADuM3402-EP
Typ
Max Unit
µA
µA
V
V
V
V
0.1
0.1
0.4
100
10
20
38
5
t
PSK
t
PSKCD
t
PSKOD
22
3
6
50
3
V
V
V
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
Test Conditions/Comments
0 V ≤ V
Ix
≤ V
DDx
V
Ex
= 0 V
+0.01 +10
−3
+0.01 +10
0.4
(V
DD1
or V
DD2
) −
0.1
(V
DD1
or V
DD2
) −
0.4
3.3
2.8
0.0
0.04
0.2
I
Ox2
= −20 µA, V
Ix
= V
IxH3
I
Ox2
= −4 mA, V
Ix
= V
IxH3
I
Ox2
= 20 µA, V
Ix
= V
IxL4
I
Ox2
= 400 µA, V
Ix
= V
IxL4
I
Ox2
= 4 mA, V
Ix
= V
IxL4
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
SWITCHING SPECIFICATIONS
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
PLH
− t
PHL
|
Change vs. Temperature
Propagation Delay Skew
Channel to Channel Matching
Codirectional Channels
Opposing Directional Channels
For All Models
Output Propagation Delay
Disable (High/Low to High Impedance)
Enable (High Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
5
Logic High Output
Logic Low Output
Refresh Rate
Dynamic Supply Current per Channel
6
Input
Output
1
PW
t
PHL
, t
PLH
PWD
t
PHZ
, t
PLH
t
PZH
, t
PZL
t
R
/t
F
|CM
H
|
|CM
L
|
f
r
I
DDI (D)
I
DDO (D)
25
25
6
6
3
35
35
1.1
0.10
0.03
8
8
ns
ns
ns
kV/µs
kV/µs
Mbps
mA/Mbps
mA/Mbps
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
V
Ix
= V
DD1
/V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See
Figure 11 through Figure 15 for total V
DD1
and V
DD2
supply currents as a function of data rate for
ADuM3400-EP/ADuM3401-EP/ADuM3402-EP
channel configurations.
2
I
Ox
is the Channel x output current, where x = A, B, C, or D.
3
V
IxH
is the input side logic high.
4
V
IxL
is the input side logic low.
5
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
OUT
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
OUT
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The
transient magnitude is the range over which the common mode is slewed.
6
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per channel supply current for unloaded and loaded conditions.
