Chip Scale PAL/NTSC Video Encoder with
Advanced Power Management
ADV7174/ADV7179
FEATURES
Programmable subcarrier frequency and phase
1
ITU-R BT601/BT656 YCrCb to PAL/NTSC video encoder
Programmable LUMA delay
High quality 10-bit video DACs
Individual on/off control of each DAC
SSAF™ (super sub-alias filter)
CCIR and square pixel operation
Advanced power management features
Integrated subcarrier locking to external video source
CGMS (copy generation management system)
Color signal control/burst signal control
WSS (wide screen signaling)
Interlaced/noninterlaced operation
2
3
NTSC M, PAL N , PAL B/D/G/H/I, PAL-M , PAL 60
Complete on-chip video timing generator
Single 27 MHz clock required (×2 oversampling)
Programmable multimode master/slave operation
Macrovision 7.1 (ADV7174 only)
Closed captioning support
80 dB video SNR
Teletext insertion port (PAL-WST)
32-bit direct digital synthesizer for color subcarrier
On-board color bar generation
Multistandard video output support:
On-board voltage reference
Composite (CVBS)
2-wire serial MPU interface (I
2
C® compatible and fast I
2
C)
Component S-video (Y/C)
Single-supply 2.8 V and 3.3 V operation
Video input data port supports:
Small 40-lead 6 mm × 6 mm LFCSP package
CCIR-656 4:2:2 8-bit parallel input format
−40°C to +85°C at 3.3 V
Programmable simultaneous composite and S-video or RGB
−20°C to +85°C at 2.8 V
(SCART)/YPbPr video outputs
APPLICATIONS
Programmable luma filters low-pass [PAL/NTSC] notch,
Portable video applications
extended SSAF, CIF, and QCIF
Mobile phones
Programmable chroma filters (low-pass [0.65 MHz, 1.0 MHz,
Digital still cameras
1.2 MHz, and 2.0 MHz], CIF, and QCIF)
Programmable VBI (vertical blanking interval)
FUNCTIONAL BLOCK DIAGRAM
TTXREQ
TTX
M
U 10
L
T
I 10
P
L
E 10
X
E
R
ADV7174/ADV7179
V
AA
RESET
COLOR
DATA
P7–P0
8
4:2:2 TO
4:4:4
8
INTER-
POLATOR
8
Y 8
YCrCb
TO
U 8
YUV
MATRIX
V 8
ADD
SYNC
9
INTER-
POLATOR
9
PROGRAMMABLE
LUMINANCE
FILTER
10
PROGRAMMABLE
CHROMINANCE 10
FILTER
10
VIDEO TIMING
GENERATOR
I
2
C MPU PORT
REAL-TIME
CONTROL
CIRCUIT
10
POWER
MANAGEMENT
CONTROL
(SLEEP MODE)
CGMS AND WSS
INSERTION
BLOCK
TELETEXT
INSERTION
BLOCK
YUV TO
RBG
MATRIX
10
10
10
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
DAC A (PIN 29)
DAC B (PIN 28)
DAC C (PIN 24)
8
ADD
BURST 8
8
INTER-
POLATOR 8
U
V
10
VOLTAGE
REFERENCE
CIRCUIT
V
REF
R
SET
COMP
HSYNC
FIELD/VSYNC
BLANK
SIN/COS
DDS BLOCK
CLOCK
SCLOCK
SDATA
ALSB
SCRESET/RTC
GND
Figure 1.
ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
Throughout the document, N is referenced to PAL – Combination – N.
3
ADV7174 only.
The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Contact the sales office for the latest
Macrovision version available.
2
1
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved.
02980-A-001
ADV7174/ADV7179
TABLE OF CONTENTS
Specifications..................................................................................... 4
2.8 V Specifications ...................................................................... 4
2.8 V Timing Specifications ........................................................ 5
3.3 V Specifications ...................................................................... 6
3.3 V Timing Specifications ........................................................ 7
Absolute Maximum Ratings............................................................ 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
General Description ....................................................................... 11
Data Path Description................................................................ 11
Internal Filter Response ............................................................. 11
Typical Performance Characteristics ........................................... 13
Features ............................................................................................ 16
Color Bar Generation ................................................................ 16
Square Pixel Mode ...................................................................... 16
Color Signal Control .................................................................. 16
Burst Signal Control ................................................................... 16
NTSC Pedestal Control ............................................................. 16
Pixel Timing Description .......................................................... 16
8-Bit YCrCb Mode ................................................................. 16
Subcarrier Reset .......................................................................... 16
Real-Time Control ..................................................................... 16
Video Timing Description .................................................... 16
Vertical Blanking Data Insertion.......................................... 17
Mode 0 (CCIR-656): Slave Option ....................................... 17
Mode 0 (CCIR-656): Master Option ................................... 17
Mode 1: Slave Option HSYNC, BLANK, FIELD ............... 20
Mode 1: Master Option HSYNC, BLANK, FIELD ............ 21
Mode 2: Slave Option HSYNC, VSYNC, BLANK ............. 22
Mode 2: Master Option HSYNC, VSYNC, BLANK .......... 23
Mode 3: Master/Slave Option HSYNC, BLANK, FIELD . 24
Power-On Reset .......................................................................... 25
SCH Phase Mode ........................................................................ 25
MPU Port Description............................................................... 25
Register Accesses ........................................................................ 26
Register Programming ................................................................... 27
Subaddress Register (SR7–SR0) ............................................... 27
Register Select (SR5–SR0) ......................................................... 27
Mode Register 1 (MR1) ............................................................. 29
Mode Register 2 (MR2) ............................................................. 30
Mode Register 3 (MR3) ............................................................. 31
Mode Register 4 (MR4) ............................................................. 32
Timing Mode Register 0 (TR0) ................................................ 33
Timing Mode Register 1 (TR1) ................................................ 34
Subcarrier Frequency Registers 3–0 ........................................ 35
Subcarrier Phase Register .......................................................... 35
Closed Captioning Even Field Data Registers 1–0 ................ 35
Closed Captioning Odd Field Data Registers 1–0 ................. 36
NTSC Pedestal/PAL Teletext Control Registers 3–0 ............. 36
Teletext Request Control Register (TC07) .............................. 37
CGMS_WSS Register 0 (C/W0) ............................................... 37
CGMS_WSS Register 1 (C/W1) ............................................... 38
CGMS_WSS Register 2 (C/W2) ............................................... 38
Appendix 1—Board Design and Layout Considerations .......... 39
Ground Planes ............................................................................ 39
Power Planes ............................................................................... 39
Supply Decoupling ..................................................................... 40
Digital Signal Interconnect ....................................................... 40
Analog Signal Interconnect....................................................... 40
Appendix 2—Closed Captioning ................................................. 41
Rev. B | Page 2 of 52
ADV7174/ADV7179
Appendix 3—Copy Generation Management System (CGMS)
............................................................................................................42
Function of CGMS Bits ..............................................................42
Appendix 4—Wide Screen Signaling (WSS) ...............................43
Function of WSS Bits ..................................................................43
Appendix 5—Teletext .....................................................................44
Teletext Insertion.........................................................................44
Teletext Protocol ..........................................................................44
Appendix 6—Waveforms ...............................................................45
NTSC Waveforms (with Pedestal) ............................................ 45
NTSC Waveforms (without Pedestal) ...................................... 46
PAL Waveforms ........................................................................... 47
Pb Pr Waveforms......................................................................... 48
Appendix 7—Optional Output Filter ........................................... 49
Appendix 8—Recommended Register Values............................. 50
Outline Dimensions ........................................................................ 52
Ordering Guide ........................................................................... 52
REVISION HISTORY
4/09—Rev. A to Rev. B
Changes to Power-On Reset Section ............................................25
Changes to Figure 55 ......................................................................40
Changes to Figure 69, Figure 70, and Figure 72 ..........................47
Changes to Figure 81 Caption .......................................................52
Changes to Ordering Guide ...........................................................52
2/04—Changed from Rev. 0 to Rev A.
Added 2.8 V Version .......................................................... Universal
Format Updated.................................................................. Universal
Device Currents Updated on 3.3 V Specification .......... Universal
Added new Table 1 and renumbered Subsequent Tables............. 4
Added new Table 2 and Renumbered Subsequent Tables ........... 5
Change to Figure 54 ........................................................................38
Change to Figure 55 ........................................................................39
Change to Figure 79 ........................................................................48
Changed Ordering Guide Temperature Specifications ..............52
Updated Outline Dimensions ........................................................52
10/02—Revision 0: Initial Version
Rev. B | Page 3 of 52
ADV7174/ADV7179
SPECIFICATIONS
2.8 V SPECIFICATIONS
V
AA
= 2.8 V, V
REF
= 1.235 V, R
SET
= 150 Ω. All specifications T
MIN
to T
MAX 1
, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
2
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
2
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN
DIGITAL OUTPUTS
2
Output High Voltage, V
OH
Output Low Voltage, V
OL
Three-State Leakage Current
Three-State Output Capacitance
ANALOG OUTPUTS
2
Output Current
3
DAC-to-DAC Matching
Output Compliance, V
OC
Output Impedance, R
OUT
Output Capacitance, C
OUT
POWER REQUIREMENTS
2, 4
V
AA
Normal Power Mode
I
DAC
(Max)
5
I
CCT 6
Low Power Mode
I
DAC
(Max)
5
I
CCT6
Sleep Mode
I
DAC 7
I
CCT 8
Power Supply Rejection Ratio
Conditions
1
Min
Typ
Max
10
R
SET
= 300 Ω
Guaranteed monotonic
1.6
V
IN
= 0.4 V or 2.4 V
10
I
SOURCE
= 400 μA
I
SINK
= 3.2 mA
2.4
0.4
10
10
R
SET
= 150 Ω, R
L
= 37.5 Ω
33
0
30
I
OUT
= 0 mA
2.8
R
SET
= 150 Ω, R
L
= 37.5 Ω
115
30
62
30
0.1
0.001
0.01
120
30
34.7
2.0
37
1.4
0.7
±1
±3.0
±1
Unit
Bits
LSB
LSB
V
V
μA
pF
V
V
μA
pF
mA
%
V
kΩ
pF
V
mA
mA
mA
mA
μA
μA
%/%
COMP = 0.1 μF
0.5
1
2
Temperature range T
MIN
to T
MAX
: –20°C to +85°C.
Guaranteed by characterization.
3
DACs can output 35 mA typically at 2.8 V (R
SET
= 150 Ω and R
L
= 37.5 Ω). Full drive into 37.5 Ω load.
4
Power measurements are taken with clock frequency = 27 MHz. Max T
J
= 110°C.
5
I
DAC
is the total current (min corresponds to 5 mA output per DAC, max corresponds to 37 mA output per DAC) to drive all three DACs. Turning off individual DACs
reduces I
DAC
correspondingly.
6
I
CCT
(circuit current) is the continuous current required to drive the device.
7
Total DAC current in sleep mode.
8
Total continuous current during sleep mode.
Rev. B | Page 4 of 52
ADV7174/ADV7179
2.8 V TIMING SPECIFICATIONS
V
AA
= 2.8 V, V
REF
= 1.235 V, R
SET
= 150 Ω. All specifications T
MIN
to T
MAX 1
, unless otherwise noted.
Table 2.
Parameter
MPU PORT
2, 3
SCLOCK Frequency
SCLOCK High Pulse Width, t
1
SCLOCK Low Pulse Width, t
2
Hold Time (Start Condition), t
3
Setup Time (Start Condition), t
4
Data Setup Time, t
5
SDATA, SCLOCK Rise Time, t
6
SDATA, SCLOCK Fall Time, t
7
Setup Time (Stop Condition), t
8
ANALOG OUTPUTS
3, 4
Analog Output Delay
DAC Analog Output Skew
CLOCK CONTROL AND PIXEL PORT
4, 5
f
CLOCK
Clock High Time, t
9
Clock Low Time, t
10
Data Setup Time, t
11
Data Hold Time, t
12
Control Setup Time, t
11
Control Hold Time, t
12
Digital Output Access Time, t
13
Digital Output Hold Time, t
14
Pipeline Delay, t
PD 5
TELETEXT
3, 4, 6
Digital Output Access Time, t
16
Data Setup Time, t
17
Data Hold Time, t
18
RESET CONTROL
3, 4
RESET Low Time
1
2
Conditions
1
Min
0
0.6
1.3
0.6
0.6
100
Typ
Max
400
Unit
kHz
μs
μs
μs
μs
ns
ns
ns
μs
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
ns
ns
ns
ns
After this period the first clock is generated
Relevant for repeated start condition
300
300
0.6
7
0
27
8
8
3.5
4
4
3
12
8
48
23
2
6
6
Temperature range T
MIN
to T
MAX
: –20°C to +85°C.
TTL input values are 0 V to 2.8 V, with input rise/fall times −3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load –10 pF.
3
Guaranteed by characterization.
4
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
5
See Figure 60.
6
Teletext Port consists of the following:
Teletext Output: TTXREQ
Teletext Input: TTX
Rev. B | Page 5 of 52
