AFBR-59E4APZ
Multimode Small Form Factor (SFF) Transceiver
for Fast Ethernet, with LC connector
Data Sheet
Description
The AFBR-59E4APZ is a new power saving Small Form
Factor transceiver that gives the system designer
a product to implement a range of solutions for
multimode fiber Fast Ethernet.
This transceiver is supplied in the industry standard 2 x
5 DIP style with an LC fiber connector interface.
Features
•
Multisourced 2 x 5 package style
•
Operates with 62.5/125
µm
and 50/125
µm
multimode
fiber
•
Single +3.3 V power supply
•
Wave solder and aqueous wash process compatibil-
ity
•
Manufactured in an ISO 9001 certified facility
•
Compatible with the optical performance requirements
of 100Base-FX version of IEEE 802.3u
•
RoHS compliant
•
LVPECL Signal Detect Output
•
Temperature range: -40
°C
to +85
°C
Transmitter
The transmitter section of the AFBR-59E4APZ transceiv-
er utilizes a 1310 nm LED. This LED is packaged in the
optical subassembly portion of the transmitter section.
It is driven by an integrated circuit that converts differ-
ential LVPECL logical signals into an analog LED drive
current.
Application
•
Fast Ethernet
Receiver
The receiver utilizes an InGaAs PIN photodiode coupled
to a trans-impedance pre-amplifier IC. It is packaged in
the optical subassembly of the receiver. The PIN/pre-
amplifier combination is connected to a quantizer IC,
which provides the final pulse shaping for data output.
The data output is differential LVPECL. The Signal Detect
output is single-ended. Both Data and Signal Detect
outputs are LVPECL compatible.
Package
The package outline drawing and pinout are shown
in Figure 1 and Figure 5. The details of this package
outline and pinout are compliant with the multisource
definition of the 2 x 5 DIP. The low profile of the Avago
transceiver design complies with the maximum height
allowed for the LC connector over the entire length of
the package.
The optical subassemblies utilize a high-volume
assembly process together with low-cost lens elements,
which result in a cost-effective building block.
The electrical subassembly consists of a high volume
multilayer printed circuit board on which the ICs and
various surface-mounted passive circuit elements are
attached.
The receiver and transmitter sections include an
internal shield for the electrical and optical subassem-
blies to ensure high immunity to external EMI fields.
The outer housing including the LC ports is molded
of filled nonconductive plastic to provide mechani-
cal strength. The solder posts of the Avago design are
isolated from the internal circuit of the transceiver.
The transceiver is attached to a printed circuit board
with the ten signal pins and the two solder posts, which
exit the bottom of the housing. The two solder posts
provide the primary mechanical strength to withstand
the loads imposed on the transceiver by mating with
the LC connector fiber cables.
Pin Descriptions
Pin 1 Receiver Signal Ground V
EE
RX:
Directly connect this pin to the receiver ground plane.
Pin 2 Receiver Power Supply V
CC
RX:
Provide +3.3 V DC via the recommended receiver power
supply filter circuit. Locate the power supply filter
circuit as close as possible to the V
CC
RX pin.
Pin 3 Signal Detect SD:
Normal optical input levels to the receiver result in a
logic “1” output.
Low optical input levels to the receiver result in a logic
“0” output.
Pin 4 Receiver Data Out Bar RD-:
Signal AC coupled LVPECL. See Figure 2.
Pin 5 Receiver Data Out RD+:
Signal AC coupled LVPECL. See Figure 2.
Pin 6 Transmitter Power Supply V
CC
TX:
Provide +3.3 V DC via the recommended transmitter
power supply filter circuit. Locate the power supply
filter circuit as close as possible to the V
CC
TX pin.
Pin 7 Transmitter Signal Ground V
EE
TX:
Directly connect this pin to the transmitter ground
plane.
RX
TX
Mounting
Studs/Solder
Posts
Pin 8 NC:
Not connected.
Pin 9 Transmitter Data In TD+:
Signal AC coupled LVPECL. See Figure 2.
Top
View
Pin 10 Transmitter Data In Bar TD-:
Signal AC coupled LVPECL. See Figure 2.
Mounting Studs/Solder Posts
RECEIVER SIGNAL GROUND
RECEIVER POWER SUPPLY
SIGNAL DETECT
RECEIVER DATA OUT BAR
RECEIVER DATA OUT
o
o
o
o
o
1
2
3
4
5
10
9
8
7
6
o
o
o
o
o
TRANSMITTER DATA IN BAR
TRANSMITTER DATA IN
NC
TRANSMITTER SIGNAL GROUND
TRANSMITTER POWER SUPPLY
The mounting studs are provided for transceiver me-
chanical attachment to the circuit board. It is recom-
mended that you connect the holes in the circuit board
to chassis ground.
Figure 1. Pin Out Diagram
2
Application Information
The Applications Engineering group is available to
assist you with the technical understanding and design
trade-offs associated with these transceivers. You can
contact them through your Avago sales representative.
The following information is provided to answer some
of the most common questions about the use of these
parts.
Shipping Container
The transceiver is packaged in a shipping container
designed to protect it from mechanical and ESD
damage during shipment of storage.
Board Layout - Decoupling Circuit, Ground Planes and
Termination Circuits
To achieve optimum performance from these trans-
ceivers, do take care in the layout of your circuit board.
Figure 2 provides a schematic for a recommended ter-
mination circuit that works well with these parts, It
is further recommended that a contiguous ground
plane be provided in the circuit board directly under
the transceiver to provide a low-inductance ground
for signal return current. This recommendation is
in keeping with good high frequency board layout
practices. Figure 3 shows a recommended power
supply filter.
Transceiver Optical Power Budget versus Link Length
Optical Power Budget (OPB) is the available optical
power for a fiber optic link to accommodate fiber cable
losses plus losses due to in-line connectors, splices,
optical switches, and to provide margin for link aging
and unplanned losses due to cable plant reconfigura-
tion or repair.
Avago LED technology has produced 1300 nm LED
devices with lower aging characteristics than normally
associated with these technologies in the industry.
The industry convention is 1.5 dB aging for 1300 nm
LEDs. The 1300 nm Avago LEDs are specified to expe-
rience less than 1 dB of aging over normal commercial
equipment mission life periods. Contact your Avago
sales representative for additional details.
Board Layout - Hole Pattern
The Avago transceiver complies with the circuit board
“Common Transceiver Footprint” hole pattern defined
in the original multisource announcement that defined
the 2 x 5 package style. This drawing is reproduced in
Figure 5 with the addition of ANSI Y14.5M compliant
dimensioning to be used as a guide in the mechani-
cal layout of your circuit board. Figure 5 illustrates the
recommended panel opening and the position of the
circuit board with respect to this panel.
Recommended Handing Precautions
Avago recommends that normal status precautions be
taken in the handling and assembly of these transceiv-
ers to prevent damage, which may be induced by elec-
trostatic discharge (ESD). The AFBR-59E4APZ transceiv-
er meets Jedec JESD22-A114 Class 2 products.
Care should be used to avoid shorting the receiver data
or signal detect outputs directly to ground without
proper current limiting impedance.
Regulatory Compliance
These transceiver products are intended to enable
commercial system designers to develop equipment
that complies with the various international regula-
tions governing certification of Information Technology
Equipment. See the Regulatory Compliance Table for
details. Additional information is available from your
Avago sales representative.
Solder and Wash Process Compatibility
The transceivers are delivered with protective process
plugs inserted into the LC receptacle.
This process plug protects the optical subassemblies
during wave solder and aqueous wash processing, and
acts as a dust cover during shipping.
These transceivers are compatible with either industry
standard wave or hand solder processes.
3
AFBR-59E4APZ
SerDes IC
(AC Coupling Data)
50
Ω
i
TX+
100 nF
TX-
100 nF
50
Ω
i
100
Ω
LED Driver
LED
3.3 V
2.7 kΩ
100
Ω
2.7 kΩ
50
Ω
i
RX+
100 nF
RX-
100 nF
50
Ω
i
AMPLIFIER &
QUANTIZER
150
Ω
GND
PD
4.3 kΩ
4.3 kΩ
150
Ω
SD
10 kΩ
GND
Control Logic
PECL input
GND
Note:
Refer to SerDes supplier's recommendation regarding the interface between AFBR-59E4APZ and SerDes.
The proposed termination is recommended for LVPECL AC-coupled signals.
Other terminations could also be applicable, depending on the SerDes interface.
Figure 2. Recommended Termination Circuit
AFBR-59E4APZ
Vcc TX
1
µH
0.1
µF
1
µH
0.1
µF
10
µF
0.1
µF
10
µF
Vcc RX
3.3V
Note:
Inductors should have less than 1
Ω
series resistor per MSA.
Figure 3. Recommended Power Supply Filter
4
All dimensions are in millimeters (inches).
Figure 4. Package Outline Drawing
5
