Am29LV033C
32 Megabit (4 M x 8-Bit)
CMOS 3.0 Volt-only Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
SOFTWARE FEATURES
s
Zero Power Operation
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly zero
s
Supports Common Flash Memory Interface (CFI)
s
Erase Suspend/Erase Resume
— Suspends erase operations to allow programming
in same bank
s
Package options
— 63-ball FBGA
— 40-pin TSOP
s
Data# Polling and Toggle Bits
— Provides a software method of detecting the status
of program or erase cycles
s
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash standard
s
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
s
Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
s
Any combination of sectors can be erased
s
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
cycle completion
s
Flexible sector architecture
— Sixty-four 64 Kbyte sectors
s
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to the read mode
s
Manufactured on 0.32 µm process technology
PERFORMANCE CHARACTERISTICS
s
ACC input pin
— Acceleration (ACC) function provides accelerated
program times
s
High performance
— Access times as fast as 70 ns
— Program time: 7 µs/byte typical utilizing Accelerate
function
s
Sector protection
— Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within that
sector
— Temporary Sector Unprotect allows changing data
in protected sectors in-system
s
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
s
Minimum 1 million write cycles guaranteed
per sector
s
20-year data retention at 125°C
— Reliable operation for the life of the system
s
Command sequence optimized for mass storage
— Specific addresses not required for unlock cycles
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
22268
Rev:
B
Amendment/+2
Issue Date:
Novembe 7, 2000
GENERAL DESCRIPTION
The Am29LV033C is a 32 Mbit, 3.0 Volt-only Flash
memory organized as 4,194,304 bytes. The device is
offered in 63-ball FBGA and 40-pin TSOP packages.
The byte-wide (x8) data appears on DQ7–DQ0. All
read, program, and erase operations are accomplished
using only a single power supply. The device can also
be programmed in standard EPROM programmers.
The standard device offers access times of 70, 90, and
120 ns, allowing high speed microprocessors to oper-
ate without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The device requires only a
single 3.0 volt power sup-
ply
for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The
Unlock Bypass
mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits.
After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to
the system reset circuitry. A system reset would thus
also reset the device, enabling the system micropro-
cessor to read the boot-up firmware from the Flash
memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly re-
duced in both these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
2
Am29LV033C
TABLE OF CONTENTS
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 2
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Standard Products .................................................. 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29LV033C Device Bus Operations ............9
Figure 5. Data# Polling Algorithm................................ 24
RY/BY#: Ready/Busy# ......................................... 25
DQ6: Toggle Bit I .................................................. 25
DQ2: Toggle Bit II ................................................. 25
Reading Toggle Bits DQ6/DQ2 ............................ 25
DQ5: Exceeded Timing Limits .............................. 26
DQ3: Sector Erase Timer ..................................... 26
Figure 6. Toggle Bit Algorithm..................................... 26
Table 10. Write Operation Status ................................27
Requirements for Reading Array Data ................... 9
Writing Commands/Command Sequences ............ 9
Accelerated Program Operation ........................... 10
Program and Erase Operation Status .................. 10
Standby Mode ...................................................... 10
Automatic Sleep Mode ......................................... 10
RESET#: Hardware Reset Pin ............................. 10
Output Disable Mode ............................................ 11
Table 2. Am29LV033C Sector Address Table ............11
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 28
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 28
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29
CMOS Compatible ............................................... 29
Zero Power Flash ................................................. 30
Figure 9. I
CC1
Current vs. Time (Showing Active
and Automatic Sleep Currents) ................................... 30
Figure 10. Typical I
CC1
vs. Frequency ......................... 30
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11. Test Setup.................................................. 31
Table 11. Test Specifications ......................................31
Autoselect Mode ................................................... 13
Table 3. Am29LV033C Autoselect Codes
(High Voltage Method) ................................................13
Key to Switching Waveforms . . . . . . . . . . . . . . . 31
Figure 12. Input Waveforms and
Measurement Levels ................................................... 31
Sector/Sector Block Protection and Unprotection 13
Table 4. Sector Block Addresses for
Protection/Unprotection ...............................................14
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32
Read Operations .................................................. 32
Figure 13. Read Operations Timings .......................... 32
Temporary Sector/Sector Block Unprotect ........... 14
Figure 1. Temporary Sector Unprotect Operation....... 14
Figure 2. In-System Sector Protect/
Unprotect Algorithms................................................... 15
Hardware Reset (RESET#) .................................. 33
Figure 14. RESET# Timings........................................ 33
Erase/Program Operations ................................... 34
Figure 15. Program Operation Timings ....................... 35
Figure 16. Accelerated Program Timing Diagram ....... 35
Figure 17. Chip/Sector Erase Operation Timings........ 36
Figure 18. Data# Polling Timings (During
Embedded Algorithms)................................................ 37
Figure 19. Toggle Bit Timings (During
Embedded Algorithms)................................................ 37
Figure 20. DQ2 vs. DQ6.............................................. 37
Figure 21. Temporary Sector/Sector
Block Unprotect Timing Diagram................................. 38
Figure 22. Sector Protect/Unprotect
Timing Diagram ........................................................... 39
Figure 23. Alternate CE# Controlled Write
Operation Timings ....................................................... 41
Hardware Data Protection .................................... 16
Low V
CC
Write Inhibit ............................................ 16
Write Pulse “Glitch” Protection ............................. 16
Logical Inhibit ....................................................... 16
Power-Up Write Inhibit ......................................... 16
Common Flash Memory Interface (CFI) . . . . . . . 16
Table 5. CFI Query Identification String ......................16
Table 6. System Interface String .................................17
Table 7. Device Geometry Definition ..........................17
Table 8. Primary Vendor-Specific Extended Query ....18
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 19
Reading Array Data .............................................. 19
Reset Command .................................................. 19
Autoselect Command Sequence .......................... 19
Byte Program Command Sequence ..................... 19
Unlock Bypass Command Sequence ................... 20
Accelerated Program Operations ......................... 20
Figure 3. Program Operation ...................................... 20
Chip Erase Command Sequence ......................... 20
Sector Erase Command Sequence ...................... 21
Erase Suspend/Erase Resume Commands ......... 21
Figure 4. Erase Operation........................................... 22
Table 9. Am29LV033C Command Definitions ...........23
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 24
DQ7: Data# Polling ............................................... 24
Erase and Programming Performance . . . . . . . 42
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 42
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 42
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 43
TS 040—40-Pin Standard TSOP ......................... 43
TSR040—40-Pin Reverse TSOP ........................ 44
FBD063—63-Ball Fine-Pitch Ball Grid Array
(FBGA) 8 x 14 mm ............................................... 45
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 46
Revision B (January 3, 2000) ............................... 46
Revision B+1 (February 21, 2000) ....................... 46
Revision B+2 (November 7, 2000) ....................... 46
Am29LV033C
3
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Option
Max Access Time (ns)
CE# Access (ns)
OE# Access (ns)
Full Voltage Range: V
CC
= 2.7–3.6 V
-70
70
70
30
Am29LV033C
-90
90
90
40
-120
120
120
50
Note:
See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
RY/BY#
V
CC
V
SS
RESET#
Erase Voltage
Generator
Input/Output
Buffers
Sector Switches
DQ0
–
DQ7
WE#
ACC
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE#
OE#
STB
V
CC
Detector
Timer
Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0–A21
4
Am29LV033C
CONNECTION DIAGRAMS
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
ACC
RY/BY#
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
V
SS
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
V
CC
V
CC
A21
DQ3
DQ2
DQ1
DQ0
OE#
V
SS
CE#
A0
40-Pin Standard TSOP
A17
V
SS
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
V
CC
V
CC
A21
DQ3
DQ2
DQ1
DQ0
OE#
V
SS
CE#
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40-Pin Reverse TSOP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
ACC
RY/BY#
A18
A7
A6
A5
A4
A3
A2
A1
Am29LV033C
5
