erase-before-write capability. Only when the chip is
in the write enable state and proper Vcc operation
range is the write instruction accepted and thus to
protect against inadvertent writes. Data is written in
16 bits per write instruction into the selected
register. If chip select (CS) is brought high after
initiation of the write cycle, the data output (DO) pin
will indicate the read/busy status of the chip.
The AM93LC86 is available in space-saving 8-lead
PDIP, SOP and TSSOP packages.
Pin Assignments
CS
SK
DI
DO
1
2
3
4
8
7
6
5
Pin Descriptions
(note)
1
2
3
4
8
7
6
5
VCC
WP
ORG
GND
CS
SK
DI
DO
VCC
WP
ORG
GND
PDIP Package
CS
SK
DI
DO
1
2
3
4
8
7
6
5
SOP Package
VCC
WP
ORG
GND
Name
CS
SK
DI
DO
GND
VCC
WP
ORG
Description
Chip select
Serial clock
Data input
Data output
Ground
Power supply
Write protection (active low)
Organization
Note:
See pin descriptions (continued) for more details
TSSOP Package
Ordering Information
AM93 LC 86 X X X
Operating Voltage
LC : 2.7V~5.5V,CMOS
Type
86: 16K
Temp. grade
o
o
Blank :
0 Co~
+
70 Co
I :
−
40 C ~
+
85 C
Package
S : SOP-8L
N : PDIP-8L
TS: TSSOP-8L
Packing
Blank : Tube
A : Taping
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev 0.1 Oct 20, 2003
1/12
AM93LC86
16384-bits Serial Electrically Erasable PROM
Block Diagram
(Preliminary)
Data register
Dummy bit
DO
DI
Instruction
register
(13/14 bits)
R/W AMPS
CS
Instruction
decode control
and
clock generation
Address register
Decoder
EEPROM
array
(1024 X 16)
or
(2048 X 8)
VCC
SK
V
CC
range
detector
WP
Write enable
High voltage
generator
GND
ORG
Absolute Maximum Ratings
Symbol
T
STG
V
CC
T
OP
Parameter
Storage temperature
Voltage with respect to ground
Temperature under bias
Rating
-65 to +125
-0.3 to + 6.5
0 to + 70
Unit
°C
V
°C
Note:
These are stress rating only. Appropriate conditions for operating these devices given elsewhere may permanently damage the
part. Prolonged exposure to maximum ratings may affect device reliability.
Anachip Corp.
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2/12
Rev 0.1 Oct 20, 2003
AM93LC86
16384-bits Serial Electrically Erasable PROM
(Preliminary)
DC Electrical Characteristics
(Vcc =2.7~5.5V, T
A
= 25
o
C, unless otherwise noted)
Symbol
I
CC
I
SB
I
IL
I
OL
V
IL
V
IH
V
OL1
V
OH1
V
OL2
V
OL2
Parameter
Operating current**
Standby current
Input leakage
Output leakage
Input low voltage**
Input high voltage**
Output low voltage
Output high voltage
Output low voltage
Output high voltage
Conditions
CS=V
IH
, SK=1MHz CMOS input levels
CS=DI=SK=0V
V
IN
= 0V to V
CC(CS,SK,DI)
V
OUT
= 0V to V
CC
, CS=0V
V
CC
= 3V + 10%
V
CC
= 5V + 10%
V
CC
= 3V + 10%
V
CC
= 5V + 10%
I
OL
= 2.1mA TTL, V
CC
=5V + 10%
I
OH
= -400uA TTL, V
CC
=5V + 10%
I
OL
= 10uA CMOS
I
OH
= -10uA CMOS
Min
Max
3
10
1
1
0.15 V
CC
0.8
V
CC
+0.2
V
CC
+0.2
0.4
0.2
V
CC
-0.2
Unit
mA
µA
µA
µA
V
V
V
V
V
V
-1
-1
-0.1
-0.1
0.8 V
CC
2
2.4
Note ** :
I
CC
, V
IL
min and V
IH
max are for reference only and are not tested.
AC Electrical Characteristics
(Vcc = 2.7V ~ 5.5V, T
A
= 25
o
C, unless otherwise noted)
Symbol
F
SK
T
SKH
T
SKL
T
CS
T
CSS
T
DIS
T
CSH
T
DIH
T
PD1
T
PD0
T
SV
T
DF
T
WP
Endurance
(note)
Parameter
SK Clock Frequency
SK High Time
SK Low Time
Minimum CS Low Time
CS Setup Time
DI Setup Time
CS Hold Time
DI Hold Time
Output Delay to "1"
Output Delay to "0"
CS to Status Valid
CS to DO in 3-state
Write Cycle Time
5V, 25ºC
Conditions
Min
0
250
250
250
50
100
0
100
Max
1
Unit
Mhz
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
mS
write cycles
Relative to SK
Relative to SK
Relative to SK
Relative to SK
AC test (Fig. 1)
AC test (Fig. 1)
AC test CL = 100pF
CS = VIL
500
500
500
100
10
1M
Note:
The parameter is characterized and isn’t 100% tested.
1.247V
(1 TTL Gate Load)
632 ohm
DO
100PF
Figure 1. AC test circuit
Anachip Corp.
www.anachip.com.tw
3/12
Rev 0.1 Oct 20, 2003
AM93LC86
16384-bits Serial Electrically Erasable PROM
Pin Capacitance
(note)
(T
A
=25°C, F=1Mhz )
Symbol
C
OUT
C
IN
Parameter
Output capacitance
Input capacitance
Max
5
5
Unit
pF
pF
(Preliminary)
Note:
The parameter is characterized and isn’t 100% tested.
Instruction Set
Instruction
READ
EWEN
WRITE
WRAL
EWDS
ERASE
ERAL
Note:
READ: Read
EWEN: Erase/write enable
WRITE: Write
WRAL: Write all
(note)
Start bit
1
1
1
1
1
1
1
Op code
10
00
01
00
00
11
00
Address
X8
A
10
~ A
0
11XXXXXXXXX
A
10
~ A
0
01XXXXXXXXX
00XXXXXXXXX
A
10
~ A
0
10XXXXXXXXX
X16
A
9
~ A
0
11XXXXXXXX
A
9
~ A
0
01XXXXXXXX
00XXXXXXXX
A
9
~ A
0
10XXXXXXXX
Input data
×
8
×
16
-
-
-
-
D
7
– D
0
D
15
- D
0
D
7
– D
0
D
15
- D
0
-
-
-
-
-
-
EWDS: Erase/write disable
ERASE: Erase
ERAL: Erase all
Functional Description
Endurance and data retention
The AM93LC86 is designed for applications
requiring up to 1M programming cycles (WRITE,
WRAL, EARSE and ERAL). It provides 40 years of
secure data retention.
Device operation
The AM93LC86 is controlled by seven 13-bit
instructions. Instructions are clocked in (serially) on
the DI pin. Each instruction begins with a logical "1"
(the start bit). This is followed by the opcode (2 bits),
the address field (10/11 bits), and data, if
appropriated,. The clock signal (SK) may be halted
at any time and the AM93LC86 will remain in its last
state. This allows full static flexibility and maximum
power conservation.
Auto increment read operations
Sequential read is possible, since the AM93LC86
has been designed to output a continuous stream
of memory content in response to a single
read
operation instruction. To utilize this function, the
system asserts a read instruction specifying a start
location address. Once the 8-bit or 16-bit of the
addressed word have been clocked out, the data in
consecutively higher address locations is output.
The address will wrap around continuously with CS
high until the chip select (CS) control pin is brought
low. This allows for single instruction data dumps to
be executed with a minimum of firmware overhead.
Read (READ)
The READ instruction is the only instruction that
outputs serial data on the DO pin. After the read
instruction and address have been decoded, data is
transferred from the selected memory register into
a 8-bit or 16-bit serial shift register. (Please note
that one logical "0" bit precedes the actual 8-bit or
16-bit output data string.) The output on DO
changes during the rising edge transitions of SK.
(shown in figure 3)
Anachip Corp.
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4/12
Rev 0.1 Oct 20, 2003
AM93LC86
16384-bits Serial Electrically Erasable PROM
Functional Description
Erase/write enable (EWEN)
Before any device programming (WRITE, WRAL,
ERASE, and ERAL) can be done, the EWEN
instruction must be executed first. When Vcc is
applied, this device powers up in the EWDS state.
The device then remains in a erase/write disable
(EWDS) state until a EWEN instruction is executed.
Thereafter the device remains enabled until a
EWDS instruction is executed or until Vcc is
removed. (shown in Figure 4)
Note: Neither the EWEN nor the EWDS instruction
has any effect on the READ instruction.
Erase/write disable (EWDS)
The erase/write disable (EWDS) instruction
disables all programming capabilities. This protects
the entire part against accidental modification of
data until a EWEN instruction is executed. (When
Vcc is applied, this part powers up in the EWDS
state.) To protect data, a EWDS instruction should
be executed upon completion of each programming
operation.
Note:
Neither the EWEN nor the EWDS instruction has any effect on
the READ instruction. (shown in figure 5)
(Preliminary)
Before a WRITE instruction can be executed, the
device must be in the Write enable (WEN) state.
Write all (WRAL)
The Write All (WRAL) instruction programs all
registers with the data pattern specified in the
instruction. While the WRAL instruction is being
loaded, the address field becomes a sequence of
DON'T-CARE bits. (Shown in Figure 7)
As with the WRITE instruction, if CS is brought
HIGH after a minimum wait of 250ns (tcs), the DO
pin indicates the READY/BUSY status of the chip.
(shown in figure 7)
Erase (ERASE)
After the erase instruction is entered, CS must be
