applications where efficiency is important. Internal
level-shift, high-side drive circuitry, and preset
shoot-thru control, allows the use of inexpensive
N-channel power switches.
AP2002 features include temperature compensated
voltage reference, an internal 200Khz virtual
frequency oscillator, under voltage lockout
protection, soft-start function and current sense
comparator circuitry.
Power good signaling,
shutdown, and over voltage protection are also
provided by AP2002.
Applications
- Microprocessor core supply
- Low cost synchronous applications
- Voltage Regulator Modules (VRM)
- DDR termination supplies
- Networking power supplies
- Sequenced power supplies
Pin Assignment
(Top View)
VCC
PWRGD
OVP
OCSET
PHASE
DRVH
PGND
1
2
3
5
6
7
14
13
12
10
Pin Descriptions
GND
SS/SHDN
COMP
SENSE
BSTH
BSTL
DRVL
Name
VCC
PWRGD
OVP
OCSET
PHASE
DRVH
PGND
DRVL
BSTL
BSTH
SENSE
COMP
SS/
SHDN
GND
Description
Chip supply voltage
Logic high indicates correct output
voltage (open drain output)
Over voltage protection
Sets the converter over-current trip
point
Input from the phase node between
the MOSFETs
High side driver output
Power ground
Low side driver output
Bootstrap, low side driver
Bootstrap, high side driver
Voltage sense input
Compensation pin
Soft start, a capacitor to ground sets
the slow start time
Signal ground
4
AP2002
11
9
8
SOP-14L
Ordering Information
AP2002 X
Package
S: SOP-14L
X
X
Lead Free
Packing
Blank : Tube
Blank : Normal
L : Lead Free Package A : Taping
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev. 0.2 Apr 14, 2004
1/7
AP2002
Synchronous PWM Controller
Block Diagram
VCC
+10%
- 10%
0.8V
+20%
Vbg
Under
Voltage
+
-
Oscillator
+
-
200uA
Over Current
+
-
OCSET
PWRGD
Vcc
OVP
COMP
SENSE
Vbg
Vcc
10uA
SS/SHDN
2uA
GND
0.5V
Absolute Maximum Ratings
Symbol
V
IN
V
PHASE
Θ
JC
Θ
JA
T
OP
T
ST
T
LEAD
PGND to GND
PHASE to GND
BSTH to PHASE
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering) 10 Sec.
Parameter
VCC, BSTL to GND
Max.
-1 to 14
+ 0.5
-1 to 18
14
45
115
-40 to +85
-65 to +150
300
o
o
Anachip Corp.
www.anachip.com.tw
2/7
+
-
+
-
+
-
One-Shot
Error Amp
PWM
DRVH
BSTH
DRVH
S
R Ob
Foult
0.6V
+
-
Cross
Current
Control
PHASE
VCC
BSTL
DRVL
PGND
+
-
DRVL
Unit
V
V
V
V
C/W
C/W
o
o
o
C
C
C
Rev. 0.2 Apr 14, 2004
AP2002
Synchronous PWM Controller
Electrical Characteristics
Symbol
Power Supply
V
CC
I
CC
∆V
LINE
Error Amplifier
A
OL
I
B
Oscillator
F
OSC
DC
MAX
I
DRVH
I
DRVL
Protection
D
TH
I
OVP
D
PG
T
DEAD
I
OCSET
Reference
V
REF
Soft Start
I
SSC
Charge Current
V
SS
= 1.5V
V
SS
= 1.5V
8.0
1.3
10
2
4.2
I
O(REF)
= 0.1mA
T
A
= 25ºC
4.0
200
12
2.7
4.4
uA
uA
V
V
mV
I
SSD
Discharge Current
Under voltage lockout (UVLO)
Upper threshold voltage
V
UT
(V
CC
)
Lower threshold voltage
V
LWT
(V
CC
)
V
HT
Hysteresis (V
CC
)
Reference Voltage
Accuracy
0
o
C to 70
o
C
0.792
-1
0.8
0.808
+1
V
%
OVP Threshold
OVP Source Current
Power Good Threshold
Dead Time
Over Current Set Isink
2.0V < V
OCSET
< 12V
V
OVP
= 3V
10
88
45
180
200
112
100
220
20
%
mA
%
nS
uA
Oscillator Frequency
Oscillator Max Duty Cycle
DRVH Source/Sink
DRVL Source/Sink
V
BSTH
– V
DRVH
=4.5V
V
DRVH
– V
PHASE
= 2V
V
BSTH
– V
DRVL
= 4.5V
V
DRVL
– V
PGND
= 2V
180
90
1
1
200
95
220
KHz
%
A
A
Gain (A
OL
)
Input Bias
50
5
8
dB
uA
Supply Voltage
Supply Current
Line Regulation
VO = 2.5V
V
CC
4.2
6
0.5
12.6
10
V
mA
%
Parameter
Unless specified: V
CC
= 4.75V to 12.6V; GND = PGND = 0V; FB = V
O
; V
BSTL
= 12V; V
BSTH-PHASE
= 12V; T
J
= 25
o
C
Conditions
Min.
Typ.
Max.
Unit
MOSFET Drivers
Note 1.
Specification refers to Typical Application Circuit.
Note 2.
This device is ESD sensitive. Use of standard ESD handling precautions is required.
Anachip Corp.
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3/7
Rev. 0.2 Apr 14, 2004
AP2002
Synchronous PWM Controller
Typical Application Circuit
(1)
+5V
R1
1k
R2
10k
C1
0.1
C2
0.1
+12V
R4
10
1 VCC
GND 14
C3
0.1
C5
0.1
C6
C7
680/ 680/
16V 16V
C8
680/
16V
+
-
V
IN
5V/12V
PWRGD
OVP
R3
1k
2 PWRGD SS/SHDN 13
3 OVP
4 OCSET
5 PHASE
6 DRVH
7 PGND
SHDN
R9
270*
R8
120
R5
1.2O
R6
1.2O
L1
Q1
PFD3000 3.3uH
Q2
PFD3000 D1
Option
Vout=2.5V
+
C10
0.1
C11
680/
16V
C12
680/
16V
C13 C14
680/ 680/
16V 16V
C9
COMP 12 R7
47k 18nF
SENSE 11
BSTH 10
BSTL 9
DRVL 8
0.1u
C4
-
R10
4.7O
Note:
*Vout =Vref x (1+R9/R8)
5V & 12V dual input circuit
(2)
+5V
R1
1k
R2
10k
C1
0.1
C2
0.1
R4
10
D2
1 VCC
GND 14
2 PWRGD SS/SHDN 13
3 OVP
4 OCSET
5 PHASE
6 DRVH
7 PGND
COMP 12
SENSE 11
BSTH 10
BSTL
DRVL
9
8
C4 0.1u
R5
1.2
Ω
R6
1.2
Ω
R10
4.7
Ω
C9
Q1
L1
0.1
PFD3000 3.3uH
Q2
PFD3000
D1
Option
C3
0.1
R7
47k 18nF
SHDN
C9
C5
0.1
C6
C7
680/ 680/
16V 16V
C8
680/
16V
+
-
V
IN
5V or 12V
PWRGD
OVP
R3
1k
R9
270*
R8
120
+
C10
0.1
C11 C12
680/ 680/
16V 16V
C13
680/
16V
C14 Vout=2.5V*
680/
16V
-
Note:
* Vout=Vref x (1+R9/R8)
5V or 12V input with Bootstrapped BSTH
Anachip Corp.
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4/7
Rev. 0.2 Apr 14, 2004
AP2002
Synchronous PWM Controller
Function Description
Synchronous Buck Converter
Primary V
CORE
power is provided by a synchronous,
voltage-mode pulse width modulated (PWM)
controller. This section has all the features required
to build a high efficiency synchronous buck
converter, including “Power Good” flag, shutdown,
and cycle-by-cycle current limit.
The output voltage of the synchronous converter is
set and controlled by the output of the error
amplifier. The external resistive divider reference
voltage is derived from an internal trimmed
band-gap voltage reference. The inverting input of
the error amplifier receives its voltage from the
SENSE pin.
The internal oscillator uses an on-chip capacitor
and trimmed precision current sources to set the
oscillation frequency to 200KHz. The triangular
output of the oscillator sets the reference voltage at
the inverting input of the comparator. When the
oscillator output voltage drops below the error
amplifier output voltage, the comparator output
goes high. This pulls DRVL low, turning off the
low-side FET, and DRVH is pulled high, turning on
the high-side FET (once the cross-current control
allows it). When the oscillator voltage rises back
above the error amplifier output voltage, the
comparator output goes low. This pulls DRVH low,
turning off the high-side FET, and DRVL is pulled
high, turning on the low-side FET (once the
cross-current control allows it).
As SENSE increases, the output voltage of the
error amplifier decreases. This causes a reduction
in the on-time of the high-side MOSFET connected
to DRVH, hence lowering the output voltage.
Under Voltage Lockout
The under voltage lockout circuit of the AP2002
assures that the high-side MOSFET driver outputs
remain in the off state whenever the supply voltage
drops below set parameters. Lockout occurs if V
CC
falls below 4.1V. Normal operation resumes once
V
CC
rises above 4.2V.
Over-Voltage Protection
The over-voltage protection pin (OVP) is high only
when the voltage at SENSE is 20% higher than the
target value programmed by the external resistor
divider. The OVP pin is internally connected to a
PNP’s collector.
Anachip Corp.
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5/7
Rev. 0.2 Apr 14, 2004
Power Good
The power good function is to confirm that the
regulator outputs are within +/- 10% of the
programmed level. PWRGD remains high as long
as this condition is met. PWRGD is connected to an
internal open collector NPN transistor.
Soft Start
Initially, SS/
SHDN
sources 10uA of current to
charge an external capacitor. The outputs of the
error amplifiers are clamped to a voltage
proportional to the voltage on SS/
SHDN
. This limits
the on-time of the high-side MOSFET, thus leading
to a controlled ramp-up of the output voltages.
R
DS(ON)
Current Limiting
The current limit threshold is setting by connecting
an external resistor from V
CC
supply to OCSET.
The voltage drop across this resistor is due to the
200uA internal sink sets the voltage at the pin.
This voltage is compared to the voltage at the
PHASE node. This comparison is made only when
the high-side drive is high to avoid false current limit
triggering due to un-contributing measurements
from the MOSFETs off-voltage. When the voltage at
PHASE is less than the voltage at OCSET, an
over-current condition occurs and the soft start
cycle is initiated. The synchronous switch turns off
