AR0130CS
1/3‐inch CMOS Digital
Image Sensor
Description
ON Semiconductor AR0130 is a 1/3−inch CMOS digital image
sensor with an active−pixel array of 1280H x 960V. It captures images
with a rolling−shutter readout. It includes sophisticated camera
functions such as auto exposure control, windowing, and both video
and single frame modes. It is programmable through a simple
two−wire serial interface. The AR0130 produces extraordinarily clear,
sharp digital pictures, and its ability to capture both continuous video
and single frames makes it the perfect choice for a wide range of
applications, including gaming systems, surveillance, and HD video.
Table 1. KEY PERFORMANCE PARAMETERS
Parameter
Optical Format
Active Pixels
Pixel Size
Color Filter Array
Shutter Type
Input Clock Range
Output Clock Maximum
Output
Parallel
Max. Frame Rates
1.2 Mp (Full FOV)
720p HD (Reduced FOV)
VGA (Full FOV)
VGA (Reduced FOV)
800 x 800 (Reduced FOV)
Responsivity at 550 nm
Monochrome
RGB Green
SNR
MAX
Dynamic Range
Supply Voltage
I/O
Digital
Analog
Power Consumption
Operating Temperature
Package Options
Typical Value
1/3-inch (6 mm)
1280 (H)
×
960 (V) = 1.2 Mp
3.75
mm
Monochrome, RGB Bayer
Electronic Rolling Shutter
6 – 50 MHz
74.25 MHz
12-bit
45 fps
60 fps
45 fps
60 fps
60 fps
6.5 V/lux−sec
5.6 V/lux−sec
44 dB
82 dB
1.8 or 2.8 V
1.8 V
2.8 V
270 mW (1280 x 720 60 fps)
–30°C to + 70°C (Ambient)
–30°C to + 80°C (Junction)
PLCC
10
×
10 mm 48-pin iLCC
Bare Die
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PLCC48 11.43
y
11.43
CASE 776AL
ILCC48 10
y
10
CASE 847AC
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Features
•
Superior Low-light Performance Both in
•
•
•
•
•
•
•
•
•
VGA Mode and HD Mode
Excellent Near IR Performance
HD Video (720p60)
On-chip AE and Statistics Engine
Auto Black Level Calibration
Context Switching
Progressive Scan
Supports 2:1 Scaling
Internal Master Clock Generated by
On−chip Phase Locked Loop (PLL)
Oscillator
Parallel Output
Applications
•
Gaming Systems
•
Video Surveillance
•
720p60 Video Applications
©
Semiconductor Components Industries, LLC, 2016
January, 2019
−
Rev. 15
1
Publication Order Number:
AR0130CS/D
AR0130CS
ORDERING INFORMATION
Table 2. ORDERABLE PART NUMBERS
Part Number
AR0130CSSC00SPBA0−DP1
AR0130CSSC00SPBA0−DR1
AR0130CSSC00SPCA0−DPBR1
AR0130CSSC00SPCA0−DRBR1
AR0130CSSC00SPCAH−GEVB
AR0130CSSC00SPCAH−S115−GEVB
AR0130CSSC00SPCAH−S213A−GEVB
AR0130CSSC00SPCAW−GEVB
AR0130CSSM00SPCA0−DRBR1
AR0130CSSM00SPCAH−S213A−GEVB
Base Description
RGB Bayer 48−Pin PLCC
RGB Bayer 48−Pin PLCC
RGB Bayer 48−Pin iLCC
RGB Bayer 48−Pin iLCC
RGB Bayer headboard iLCC
RGB Bayer headboard iLCC
RGB Bayer headboard iLCC
RGB Bayer headboard iLCC
Monochrome 48−Pin iLCC
Monochrome headboard iLCC
Dry Pack without Protective Film, Double Side BBAR Glass
Variant Description
Dry Pack with Protective Film
Dry Pack without Protective Film
Dry Pack with Protective Film, Double Side BBAR Glass
Dry Pack without Protective Film, Double Side BBAR Glass
See the ON Semiconductor Device Nomenclature
document (TND310/D) for a full description of the naming
convention used for image sensors. For reference
GENERAL DESCRIPTION
The ON Semiconductor AR0130 can be operated in its
default mode or programmed for frame size, exposure, gain,
and other parameters. The default mode output is a
960p−resolution image at 45 frames per second (fps). It
outputs 12−bit raw data over the parallel port. The device
may be operated in video (master) mode or in single frame
trigger mode.
FRAME_VALID and LINE_VALID signals are output on
dedicated pins, along with a synchronized pixel clock in
parallel mode.
FUNCTIONAL OVERVIEW
The AR0130 is a progressive−scan sensor that generates
a stream of pixel data at a constant frame rate. It uses an
on−chip, phase−locked loop (PLL) that can be optionally
enabled to generate all internal clocks from a single master
documentation, including information on evaluation kits,
please visit our web site at
www.onsemi.com.
The AR0130 includes additional features to allow
application−specific tuning: windowing and offset,
adjustable auto−exposure control, and auto black level
correction. Optional register information and histogram
statistic information can be embedded in first and last 2 lines
of the image frame.
input clock running between 6 and 50 MHz The maximum
output pixel rate is 74.25 Mp/s, corresponding to a clock rate
of 74.25 MHz. Figure 1 shows a block diagram of the sensor.
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2
AR0130CS
OTPM
Active Pixel Sensor
(APS)
Array
Memory
PLL
External
Clock
Power
Timing and Control
(Sequencer)
Auto Exposure
and Stats Engine
Trigger
Two-wire
Serial
Interface
Analog Processing and
A/D Conversion
Pixel Data Path
(Signal Processing)
Parallel
Output
Control Registers
Figure 1. Block Diagram
User interaction with the sensor is through the two−wire
serial bus, which communicates with the array control,
analog signal chain, and digital signal chain. The core of the
sensor is a 1.2 Mp Active− Pixel Sensor array. The timing
and control circuitry sequences through the rows of the
array, resetting and then reading each row in turn. In the time
interval between resetting a row and reading that row, the
pixels in the row integrate incident light. The exposure is
controlled by varying the time interval between reset and
readout. Once a row has been read, the data from the
columns is sequenced through an analog signal chain
(providing offset correction and gain), and then through an
analog−to−digital converter (ADC). The output from the
ADC is a 12−bit value for each pixel in the array. The ADC
output passes through a digital processing signal chain
(which provides further data path corrections and applies
digital gain). The pixel data are output at a rate of up to
74.25 Mp/s, in parallel to frame and line synchronization
signals.
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3
AR0130CS
Digital Digital
I/O
Core
Power
1
Power
1
PLL Analog Analog
Power
1
Power
1
Power
1
1.5 kW
2,3
1.5 kW
2
V
DD
_IO
V
DD
V
DD
_PLL
V
AA
V
AA
_PIX
Master Clock
(6
−
50 MHz)
EXTCLK
S
ADDR
S
DATA
S
CLK
TRIGGER
OE_BAR
STANDBY
RESET_BAR
Reserved
D
GND
D
OUT
[11:0]
PIXCLK
LINE_VALID
FRAME_VALID
To Controller
From Controller
A
GND
V
DD
_IO
V
DD
V
DD
_PLL
V
AA
V
AA
_PIX
Digital
Ground
Analog
Ground
Notes:
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two−wire speed.
3. This pull−up resistor is not required if the controller drives a valid logic level on S
CLK
at all times.
4. ON Semiconductor recommends that VDD_SLVS pad (only available in bare die) is left unconnected.
5. ON Semiconductor recommends that 0.1
mF
and 10
mF
decoupling capacitors for each power supply are mounted as
close as possible to the pad. Actual values and results may vary depending on layout and design considerations.
Check the AR0130 demo headboard schematics for circuit recommendations.
6. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital
power planes is minimized.
7. I/O signals voltage must be configured to match V
DD
_IO voltage to minimize any leakage current.
Figure 2. Typical Configuration: Parallel Pixel Data Interface
Table 3. PAD DESCRIPTIONS
Name
STANDBY
V
DD
_PLL
V
AA
EXTCLK
V
DD
_SLVS
D
GND
V
DD
A
GND
S
ADDR
S
CLK
S
DATA
Type
Input
Power
Power
Input
Power
Power
Power
Power
Input
Input
I/O
PLL power.
Analog power.
External input clock.
Digital power (do not connect).
Digital ground.
Digital power.
Analog ground.
Two−Wire Serial Interface address select.
Two−Wire Serial Interface clock input.
Two−Wire Serial Interface data I/O.
Description
Standby−mode enable pin (active HIGH).
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4
AR0130CS
Table 3. PAD DESCRIPTIONS
Name
V
AA
_PIX
LINE_VALID
FRAME_VALID
PIXCLK
V
DD
_IO
D
OUT
8
D
OUT
9
D
OUT
10
D
OUT
11
Reserved
D
OUT
4
D
OUT
5
D
OUT
6
D
OUT
7
TRIGGER
OE_BAR
D
OUT
0
D
OUT
1
D
OUT
2
D
OUT
3
RESET_BAR
FLASH
NC
Type
Power
Output
Output
Output
Power
Output
Output
Output
Output
Input
Output
Output
Output
Output
Input
Input
Output
Output
Output
Output
Input
Output
Input
Pixel power.
Asserted when D
OUT
line data is valid.
Asserted when D
OUT
frame data is valid.
Pixel clock out. D
OUT
is valid on rising edge of this clock.
I/O supply power.
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output (MSB)
Connect to D
GND
.
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output.
Exposure synchronization input.
Output enable (active LOW).
Parallel pixel data output (LSB)
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output.
Asynchronous reset (active LOW). All settings are restored to factory default.
Flash control output.
Do not connect.
Description
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5
单片机
