AR0238
AR0238: 1/2.7-Inch
2.1 Mp/Full HD Digital
Image Sensor
General Description
ON Semiconductor’s AR0238 is a 1/2.7-inch CMOS digital image
sensor with an active−pixel array of 1928Hx1088V. It captures images
in either linear or high dynamic range modes, with a rolling−shutter
readout. It includes sophisticated camera functions such as in−pixel
binning, windowing and both video and single frame modes. It is
designed for both low light and high dynamic range scene
performance. It is programmable through a simple two−wire serial
interface. The AR0238 produces extraordinarily clear, sharp digital
pictures, and its ability to capture both continuous video and single
frames makes it the perfect choice for a wide range of applications,
including surveillance and HD video.
Table 1. KEY PARAMETERS
Parameter
Optical format
Active pixels
Pixel size
Color filter array
Shutter type
Input clock range
Output clock maxi-
mum
Output
Serial
Parallel
Frame
rate
1080p
Typical Value
1/2.7−inch (6.6 mm)
1928(H) x 1088(V) (16:9 mode)
3.0
mm
x 3.0
mm
RGB Bayer, RGB−IR
Electronic rolling shutter and GRR
6 – 48 MHz
148.5 Mp/s (4−lane HiSPi)
74.25 Mp/s (Parallel)
HiSPi 10−, or 12−bit
10−, or 12−bit
60 fps Linear HiSPi
30 fps Linear Parallel
30 fps Line Interleaved HiSPi
15 fps Line Interleaved Parallel
4.0 V/lux−sec
41 dB
Up to 96 dB
1.8 or 2.8 V
1.8 V
2.8 V
0.3 V
−
0.6 V (SLVS), 1.7 V
−
1.9 V (HiVcm)
< 300mW Line interleaved 1080p30
<190mW 1080p30 Linear Mode
−30°C
to + 85°C Ambient
11.43x11.43 mm 48−pin mPLCC
Recon Die
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Features
•
Superior Low−light Performance
•
Latest 3.0
mm
Pixel with
•
•
•
•
•
•
•
•
•
•
•
•
•
Responsivity
SNR
MAX
Max Dynamic range
Supply
voltage
I/O
Digital
Analog
HiSPi
Power consumption
(typical)
Operating temperature
Package options
ON Semiconductor DR−Pix™ Technology
with Dual Conversion Gain
Full HD Support at up to 1080P 60 fps for
Superior Video Performance
Linear or High Dynamic Range Capture
Supports Line Interleaved T1/T2 readout to
Enable HDR Processing in ISP Chip
Support for External Mechanical Shutter
On−chip Phase−locked Loop (PLL) Oscil-
lator
Integrated Position−based Color and Lens
Shading Correction
Slave Mode for Precise Frame−rate
Control
Stereo/3D Camera Support
Statistics Engine
Data Interfaces: Four−lane Serial High−
speed Pixel Interface (HiSPi) Differential
Signaling (SLVS and HiVCM), or Parallel
Auto Black Level Calibration
High−speed Configurable Context
Switching
Temperature Sensor
Applications
•
Video Recording and Streaming
•
1080p60 (monitoring) Video Applications
•
High Dynamic Range Imaging
©
Semiconductor Components Industries, LLC, 2016
March, 2020
−
Rev. 6
1
Publication Order Number:
AR0238/D
AR0238
PLCC48 11.43x11.43 (HiSPi)
CASE 776AQ
PLCC48 11.43x11.43 (Parallel)
CASE 776AS
Table 2. ORDERING INFORMATION
Part Number
AR0238CSSC12SHRA0−DR1
AR0238CSSC12SHRA0−DP1
AR0238CSSC12SHRA0−DR
AR0238CSSC12SHRA0−DP
AR0238CSSC12SPRA0−DR
AR0238CSSC12SPRA0−DR1
AR0238CSSC12SUD20
AR0238IRSH12SUD20
AR0238CSSC12SHRAH3−GEVB
NOTE:
Product Description
RGB Color, 12 Degree CRA, mPLCC, HiSPi
RGB Color, 12 Degree CRA, mPLCC, HiSPi
RGB Color, 12 Degree CRA, mPLCC, HiSPi
RGB Color, 12 Degree CRA, mPLCC, HiSPi
RGB Color, 12 Degree CRA, mPLCC, Parallel
RGB Color, 12 Degree CRA, mPLCC, Parallel
RGB Color, 12 Degree CRA, Recon die
RGB−IR, 12 Degree CRA, Recon die
RGB Color, 12 Degree CRA, HiSPi
Orderable Product Attribute Description
Dry Pack, No Protective film, Low MOQ
Dry Pack, with Protective film, Low MOQ
Without protective film
With protective film
Without Protective Film
Dry Pack, No Protective film, Low MOQ
RGB Recon die
RGB−IR Recon die
Evaluation Board
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for
image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
GENERAL DESCRIPTION
The ON Semiconductor AR0238 can be operated in its
default mode or programmed for frame size, exposure, gain,
and other parameters. The default mode output is a 1080p−
resolution image at 60 frames per second (fps) through the
HiSPi port. In linear mode, it outputs 12−bit or 10−bit
A−Law compressed raw data, using the parallel or serial
(HiSPi) output port. In high dynamic range mode, it outputs
two exposure values that the ISP will combine into an HDR
image. The device may be operated in video (master) mode
or in single frame trigger mode.
FRAME_VALID and LINE_VALID signals are output on
dedicated pins, along with a synchronized pixel clock in
parallel mode.
The AR0238 includes additional features to allow
application−specific tuning: windowing and offset, auto
black level correction, and on−board temperature sensor.
Optional register information and histogram statistic
information can be embedded in the first and last 2 lines of
the image frame.
The AR0238 is designed to operate over a wide
temperature range of
−30°C
to +85°C ambient.
FUNCTIONAL OVERVIEW
The AR0238 is a progressive−scan sensor that generates
a stream of pixel data at a constant frame rate. It uses an
on−chip, phase−locked loop (PLL) that can be optionally
enabled to generate all internal clocks from a single master
input clock running between 6 and 48 MHz. The maximum
output pixel rate is 148.5 Mp/s, corresponding to a clock rate
of 74.25 MHz. Figure 1 shows a block diagram of the sensor
configured in linear mode, and in HDR mode.
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2
AR0238
ADC Data
12
Row Noise Correction
Black Level Correction
Test Pattern Generator
Pixel Defect Correction
12
Digital Gain and Pedestal
A−Law Compression
10 bits
12 bits
HiSPi
Parallel
Figure 1. Block Diagram of AR0238
User interaction with the sensor is through the two−wire
serial bus, which communicates with the array control,
analog signal chain, and digital signal chain. The core of the
sensor is a 2.1 Mp Active− Pixel Sensor array. The timing
and control circuitry sequences through the rows of the
array, resetting and then reading each row in turn. In the time
interval between resetting a row and reading that row, the
pixels in the row integrate incident light. The exposure is
controlled by varying the time interval between reset and
readout. Once a row has been read, the data from the
columns is sequenced through an analog signal chain
(providing offset correction and gain), and then through an
analog− to−digital converter (ADC). The output from the
ADC is a 12−bit value for each pixel in the array. The ADC
output passes through a digital processing signal chain
(which provides further data path corrections and applies
digital gain). The sensor also offers a high dynamic range
mode of operation where two images and taken using
different exposures. These images are output in from the
sensor and the ISP must combine them into one high
dynamic range image.
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3
AR0238
Digital Digital
Core
I/O
Power
1
Power
1
HiSPi Power
either 0.4 V
(SLVS) or
1.8 V (HiV
CM
)
1
PLL
Analog Analog
Power
1
Power
1
Power
1
1.5 kW
2
1.5 kW
2
V
DD
_IO
V
DD
V
DD
_SLVS
V
DD
_PLL
V
AA
V
AA
_PIX
SLVS0_P
SLVS0_N
SLVS1_P
SLVS1_N
SLVS2_P
SLVS2_N
SLVS3_P
SLVS3_N
SLVSC_P
SLVSC_N
FLASH
SHUTTER
To Controller
Master Clock
(6−48 MHz)
EXTCLK
S
ADDR
From
Controller
S
DATA
S
CLK
TRIGGER
OE_BAR
RESET_BAR
TEST
D
GND
A
GND
Digital
Ground
V
DD
_IO
V
DD
V
DD
_SLVS
V
DD
_PLL
Analog
Ground
V
AA
V
AA
_PIX
Notes:
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two−wire speed.
3. The parallel interface output pads can be left unconnected if the serial output interface is used.
4. ON Semiconductor recommends that 0.1
mF
and 10
mF
decoupling capacitors for each power supply are mounted as close as possible
to the pad. Actual values and results may vary depending on the layout and design considerations. Refer to the AR0237AT demo
headboard schematics for circuit recommendations.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is
minimized.
6. I/O signals voltage must be configured to match V
DD
_IO voltage to minimize any leakage currents.
Figure 2. Typical Configuration: Serial Four−Lane
HiSPi Interface
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4
AR0238
Digital
I/O
Power
1
Digital
Core
Power
1
PLL
Power
1
Analog
Power
1
Analog
Power
1
1.5 kW
2
Master Clock
(6−48 MHz)
1.5 kW
2
V
DD
_IO
V
DD
V
DD
_PLL
V
AA
V
AA
_PIX
EXTCLK
D
OUT
[11:0]
PIXCLK
To Controller
From
Controller
S
ADDR
S
DATA
S
CLK
TRIGGER
OE_BAR
RESET_BAR
LINE_VALID
FRAME_VALID
FLASH
SHUTTER
TEST
D
GND
A
GND
Digital
Ground
V
DD
_IO
V
DD
V
DD
_PLL
V
AA
Analog
Ground
V
AA
_PIX
Notes:
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two−wire speed.
3. The serial interface output pads can be left unconnected if the parallel output interface is used.
4. ON Semiconductor recommends that 0.1
mF
and 10
mF
decoupling capacitors for each power supply are mounted as close as possible
to the pad. Actual values and results may vary depending on the layout and design considerations. Refer to the AR0237AT demo
headboard schematics for circuit recommendations.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is
minimized.
6. I/O signals voltage must be configured to match V
DD
_IO voltage to minimize any leakage currents.
7. The EXTCLK input is limited to 6−48 MHz.
Figure 3. Typical Configuration: Parallel Pixel Data Interface
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