AR0331
AR0331 1/3‐Inch 3.1 Mp/Full
HD Digital Image Sensor
General Description
The ON Semiconductor AR0331 is a 1/3-inch CMOS digital image
sensor with an active-pixel array of 2048 (H) x 1536 (V). It captures
images in either linear or high dynamic range modes, with a
rolling-shutter readout. It includes sophisticated camera functions
such as in-pixel binning, windowing and both video and single frame
modes. It is designed for both low light and high dynamic range scene
performance. It is programmable through a simple two-wire serial
interface. The AR0331 produces extraordinarily clear, sharp digital
pictures, and its ability to capture both continuous video and single
frames makes it the perfect choice for a wide range of applications,
including surveillance and HD video.
The ON Semiconductor AR0331 can be operated in its default mode
or programmed for frame size, exposure, gain, and other parameters.
The default mode output is a 1080p-resolution image at 60 frames per
second (fps). In linear mode, it outputs 12-bit or 10-bit A-Law
compressed raw data, using either the parallel or serial (HiSPi) output
ports. In high dynamic range mode, it outputs 12-bit compressed data
using parallel output. In HiSPi mode, 12- or 14-bit compressed, or
16-bit linearized data may be output. The device may be operated in
video (master) mode or in single frame trigger mode.
FRAME_VALID and LINE_VALID signals are output on dedicated
pins, along with a synchronized pixel clock in parallel mode.
The AR0331 includes additional features to allow application-
specific tuning: windowing and offset, auto black level correction, and
on-board temperature sensor. Optional register information and
histogram statistic information can be embedded in the first and last 2
lines of the image frame.
The sensor is designed to operate in a wide temperature range
(–30°C to +85°C).
Features
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ILCC48 10x10
CASE 847AG
IBGA52 9x9
CASE 503AA
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
•
Data Interfaces: Four-lane Serial High-speed
Pixel Interface (HiSPi) Differential
Signaling (SLVS and HiV
CM
), or Parallel
•
Auto Black Level Calibration
•
High-speed Context Switching
•
Temperature Sensor
Applications
•
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•
•
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Superior Low-light Performance
Latest 2.2
μm
Pixel with ON Semiconductor A-Pix™ Technology
Full HD Support at 1080 P 60 fps for Superior Video Performance
Linear or High Dynamic Range Capture
3.1 M (4:3) and 1080 P Full HD (16:9) Images
Optional Adaptive Local Tone Mapping (ALTM)
Interleaved T1/T2 Output
Support for External Mechanical Shutter
Support for External LED or Xenon Flash
Slow-motion Video (VGA 120 fps)
On-chip Phase-locked Loop (PLL) Oscillator
Integrated Position-based Color and Lens Shading Correction
Slave Mode for Precise Frame-rate Control
Stereo/3D Camera Support
Statistics Engine
1
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Video Surveillance
Stereo Vision
Smart Vision
Automation
Machine Vision
1080p60 Video Applications
High Dynamic Range Imaging
©
Semiconductor Components Industries, LLC, 2011
March, 2017
−
Rev. 14
Publication Order Number:
AR0331/D
AR0331
Table 1. KEY PARAMETERS
Parameter
Optical Format
Typical Value
1/3-inch (5.8 mm)
Note: Sensor optical format will also work with lenses designed for
1/3.2” format.
2048 (H) x 1536 (V) (4:3, mode)
2.2
μm
x 2.2
μm
RGB Bayer
Electronic rolling shutter and GRR
6 – 48 MHz
148.5 Mp/s (4-lane HiSPi)
74.25 Mp/s (Parallel)
Serial
Parallel
Frame Rate
Responsivity
SNR
MAX
Max Dynamic Range
Supply Voltage
I/O
Digital
Analog
HiSPi
Power Consumption (Typical)
Operating Temperature (Ambient)
Package Options
Full Resolution
1080p
HiSPi 10-, 12-, 14-, or 16-bit
10-, 12-bit
30 fps
60 fps
1.9 V/lux-sec
39 dB
Up to 100 dB
1.8 or 2.8 V
1.8 V
2.8 V
0.3 V−0.6 V, 1.7 V−1.9 V
<780 mW
–30°C to +85° C
10 x 10 mm 48 pin iLCC
9.5 x 9.5 mm 63-pin iBGA
Active Pixels
Pixel Size
Color Filter Array
Shutter Type
Input Clock Range
Output Clock Maximum
Output
ORDERING INFORMATION
Table 2. AVAILABLE PART NUMBERS
Part Number
AR0331SRSC00SHCA0-DRBR
AR0331SRSC00SHCAD3-GEVK
AR0331SRSC00SHCAD-GEVK
AR0331SRSC00SHCAH-GEVB
AR0331SRSC00SUCA0-DPBR
AR0331SRSC00SUCA0-DRBR
AR0331SRSC00SUCAD3-GEVK
AR0331SRSC00SUCAD-GEVK
AR0331SRSC00SUCAH-GEVB
AR0331SRSC00XUEAD3-GEVK
AR0331SRSC00XUEAD-GEVK
AR0331SRSC00XUEAH-GEVB
AR0331SRSC00XUEE0−BY−DRBR
AR0331SRSC00XUEE0-DPBR
AR0331SRSC00XUEE0-DRBR
AR0331SRSC00XUEE0-DRBR1
Product Description
48-pin iLCC HiSPi, 0° CRA
48-pin iLCC HiSPi, 0° CRA
48-pin iLCC HiSPi, 0° CRA
48-pin iLCC HiSPi, 0° CRA
48-pin iLCC Parallel, 0° CRA
48-pin iLCC Parallel, 0° CRA
48-pin iLCC Parallel, 0° CRA
48-pin iLCC Parallel, 0° CRA
48-pin iLCC Parallel, 0° CRA
63-pin iBGA
63-pin iBGA
63-pin iBGA
63-pin iBGA, 0° CRA
63-pin iBGA, 0° CRA
63-pin iBGA, 0° CRA
63-pin iBGA, 0° CRA
Orderable Product Attribute Description
Dry Pack without Protective Film, Double Side BBAR Glass
Demo Kit 3
Demo Kit
Demo Board
Dry Pack with Protective Film, Double Side BBAR Glass
Dry Pack without Protective Film, Double Side BBAR Glass
Demo Kit 3
Demo Kit
Demo Board
Demo Kit 3
Demo Kit
Demo Board
Dry Pack without Protective Film, Double Side BBAR Glass
Dry Pack with Protective Film, Double Side BBAR Glass
Dry Pack without Protective Film, Double Side BBAR Glass
Dry Pack without Protective Film, Double Side BBAR Glass
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2
AR0331
FUNCTIONAL OVERVIEW
The AR0331 is a progressive-scan sensor that generates
a stream of pixel data at a constant frame rate. It uses an
on-chip, phase-locked loop (PLL) that can be optionally
enabled to generate all internal clocks from a single master
ADC data
12
input clock running between 6 and 48 MHz. The maximum
output pixel rate is 148.5 Mp/s, corresponding to a clock rate
of 74.25 MHz. Figure 1 shows a block diagram of the sensor.
Row noise correction
Black level correction
Test pattern generator
Pixel defect correction
Adaptive CD filter
Companding
12 bits
( HDR and Linear),
12 or 10 bits Linear
12
16, 14, or 12 bits
Motion correction and
Blue Halo filter
Parallel
HDR linearization
(ME or DLO)
Smooting filter
16
HiSPi
Digital gain and
pedestal
Figure 1. Block Diagram
User interaction with the sensor is through the two-wire
serial bus, which communicates with the array control,
analog signal chain, and digital signal chain. The core of the
sensor is a 3.1 Mp Active-pixel Sensor array. The timing and
control circuitry sequences through the rows of the array,
resetting and then reading each row in turn. In the time
interval between resetting a row and reading that row, the
pixels in the row integrate incident light. The exposure is
controlled by varying the time interval between reset and
readout. Once a row has been read, the data from the
columns is sequenced through an analog signal chain
(providing offset correction and gain), and then through an
analog-to-digital converter (ADC). The output from the
ADC is a 12-bit value for each pixel in the array. The ADC
output passes through a digital processing signal chain
(which provides further data path corrections and applies
digital gain). The sensor also offers a high dynamic range
mode of operation where multiple images are combined
on-chip to produce a single image at 16-bit per pixel value.
A compression mode is further offered to allow the 16-bit
pixel value to be transmitted to the host system as a 12-bit
value with close to zero loss in image quality.
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3
AR0331
Digital
Digital I/0 Core
Power
1
Power
1
HiSPi
Power
1
PLL
Analog Analog
Power
1
Power
1
Power
1
1.5 kW
2
V
DD
_SLVS
1.5 kW
2
V
DD
_IO V
DD
V
DD
_PLL V
AA
VAA_PIX
SLVS0_P
SLVS0_N
SLVS1_P
SLVS1_N
SLVS2_P
SLVS2_N
SLVS3_P
SLVS3_N
SLVSC_P
SLVSC_N
FLASH
SHUTTER
Master clock
(6–48 MHz)
EXTCLK
From
Controller
S
ADDR
S
DATA
SCLK
TRIGGER
OE_BAR
RESET_BAR
TEST
To
Controller
D
GND
A
GND
V
DD
_IO
V
DD
V
DD
_SLVS
V
DD
_PLL
V
AA
V
AA
_PIX
Digital
ground
Analog
ground
Notes:
1.
2.
3.
4.
All power supplies should be adequately decoupled.
ON Semiconductor recommends a resistor value of 1.5 kΩ, but a greater value may be used for slower two-wire speed.
The parallel interface output pads can be left unconnected if the serial output interface is used.
ON Semiconductor recommends that 0.1
μF
and 10
μF
decoupling capacitors for each power supply
are mounted as close as possible to the pad. Actual values and results may vary depending on layout and design
considerations. Refer to the AR0331 demo headboard schematics for circuit recommendations.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling
with the digital power planes is minimized.
6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.
Figure 2. Typical Configuration: Serial Four-Lane HiSPi Interface
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4
AR0331
Digital
Digital I/0 Core
Power
1
Power
1
PLL
Analog Analog
Power
1
Power
1
Power
1
1.5kΩ
2
Master clock
(6–48 MHz)
1.5kΩ
2
V
DD
_IO V
DD
V
DD
_PLL V
AA
VAA_PIX
EXTCLK
S
ADDR
S
DATA
SCLK
TRIGGER
OE_BAR
RESET_BAR
TEST
D
GND
D
OUT
[11:0]
PIXCLK
LINE_VALID
FRAME_VALID
FLASH
SHUTTER
To
Controller
From
Controller
A
GND
V
DD
_IO
V
DD
V
DD
_PLL
V
AA
V
AA
_PIX
Digital
ground
Analog
ground
Notes:
All power supplies should be adequately decoupled.
ON Semiconductor recommends a resistor value of 1.5 kΩ, but a greater value may be used for slower two-wire speed.
The serial interface output pads and V
DD
SLVS can be left unconnected if the parallel output interface is used.
ON Semiconductor recommends that 0.1
μF
and 10
μF
decoupling capacitors for each power supply are mounted as
close as possible to the pad. Actual values and results may vary depending on layout and design considerations. Refer
to the AR0331 demo headboard schematics for circuit recommendations.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital
power planes is minimized.
6. I/O signals voltage must be configured to match V
DD
_IO voltage to minimize any leakage currents.
7. The EXTCLK input is limited to 6−48 MHz.
1.
2.
3.
4.
Figure 3. Typical Configuration: Parallel Pixel Data Interface
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