On-chip temperature compensated self refresh (TCSR)
Partial array refresh (PAR)
Deep Power_down(DPD) mode
OPTIONS
-
-
-
-
-
-
-
Configuration: 64Mb (4 megabit x 16)
Vcc core / VccQ I/O voltage supply: 1.8V
Timing: 70ns access
Frequency: 48MHz,83 MHz, 108 MHz, 133 MHz
Standby current at 85°C : 90uA (Max)
Standby current at 25°C : 50uA (Typ)
Operating temperature range:
Industrial
: -30°C to +85°C
ORDERING INFORMATION
Product
Family
Operating
Temperature
Interface Bus
Power Dissipation
Vcc
Range
Standby
(I
SB1
, Typ.,25
o
C)
50A
2)
AS1C4M16PL-70BIN
(-30 ~ 85
o
C)
x16
1.70 ~ 1.95V
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GENERAL DESCRIPTION
64M CellularRAM products are high-speed, CMOS pseudo-static random access memory developed for low-power, portable
applications. The 64Mb CellularRAM device has a DRAM core organized as 4 Meg x 16 bits. These devices are a variation of the
industry-standard Flash control interface, with a multiplexed address/data bus. The multiplexed address and data functionality
dramatically reduce the required signal count, and increases read/write bandwidth. For seamless operation on a burst Flash bus, 64M
CellularRAM products incorporate a transparent self refresh mechanism. The hidden refresh requires no additional support from the
system memory controller and has no significant impact on device READ/WRITE performance. Two user accessible control registers
define device operation. The bus configuration register (BCR) defines how the 64M CellularRAM device interacts with the system
memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to
control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and
can be updated anytime during normal operation. Special attention has been focused on standby current consumption during self
refresh. 64M CellularRAM products include two mechanisms to minimize standby current. Partial array refresh (PAR) enables the
system to limit refresh to only that part of the DRAM array that contains essential data. Temperature compensated self refresh (TCSR)
uses an onchip sensor to adjust the refresh rate to match the device temperature-the refresh rate decreases at lower temperatures to
minimize current consumption during standby. Deep power-down (DPD) enables the system to halt the refresh operation altogether
when no vital information is stored in the device. The system configurable refresh mechanisms are accessed through the RCR. This
64M CellularRAM specification defines the industry-standard CellularRAM1.5 x16 A/D Mux feature set established by the CellularRAM
Workgroup. It includes support for both variable and fixed latency, with three output-device drive-strength settings, a variety of wrap
options, and a device ID register (DIDR).
Figure 1: FUNTIONAL BLOCK DIAGRAM - 4 meg x 16
A[21:16]
Address Decode
Logic
Refresh Configuration
Register (RCR)
Device ID Register
(DIDR)
Bus Configuration
Register (BCR)
4,096K x 16
DRAM
MEMORY
ARRAY
Input
Output
MUX
and
Buffers
A/DQ[7:0]
A/DQ[15:8]
CLK
CE#
WE#
OE#
ADV#
CRE
LB#
UB#
WAIT
Control
Logic
Internal
External
Note: Functional block diagrams illustrate simplified device operation. See pin descriptions; Bus operations table; and timing diagrams for detailed information.
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Table 1: SIGNAL DESCRIPTIONS
Symbol
A[21:16]
Type
Input
Descriptions
Address inputs: Inputs for addresses during READ and WRITE operations. Addresses are internally latched
during READ and WRITE cycles. The address lines are also used to define the value to be loaded into the
BCR or the RCR.
Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When
configured for synchronous operation, the address is latched on the first rising CLK edge when ADV# is
active. CLK must be static (HIGH or LOW) during asynchronous access READ and WRITE operations
when burst mode is enabled.
Address valid: Indiates that a valid address is present on the address inputs. Addresses are latched on the
rising edge of ADV# during asynchronous READ and WRITE operations.
Control register enable: When CRE is HIGH, WRITE operations load the RCR or BCR, and READ
operations access the RCR, BCR, or DIDR.
Chip enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into
standby or deep power-down mode.
Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled.
Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a
configuration register or to the memory array.
Lower byte enable. DQ[7:0]
Upper byte enable. DQ[15:8]
CLK
(note1)
Input
ADV#
CRE
CE#
OE#
WE#
LB#
UB#
Input
Input
Input
Input
Input
Input
Input
Address/data I/Os: These pins are a multiplexed address/data bus. As inputs for address, these pins
A/DQ[15:0] Input/Output behave as A[15:0]. A[0] is the LSB of the 16-bit word address within the CellularRAM device. Address,
RCR, and BCR values are loaded with ADV# LOW. Data is input or output when ADV# is HIGH.
WAIT
(note1)
RFU
VCC
VCCQ
VSS
VSSQ
Wait: Provides data-valid feedback during burst READ and WRITE operations. WAIT is used to arbitrate
collisions between refresh and READ/WRITE operations. WAIT is also asserted at the end of row unless
wrapping within the burst length. Wait should be ignored during asynchronous operations. WAIT is High-Z
when CE# is HIGH.
Reserved for future use.
Device power supply: (1.70V.1.95V) Power supply for device core operation.
I/O power supply: (1.70V.1.95V) Power supply for input/output buffers.
VSS must be connected to ground.
VSSQ must be connected to ground.
Output
-
Supply
Supply
Supply
Supply
Note:
1. When using asynchronous mode exclusively, CLK can be tied to VSSQ or VCCQ. WAIT should be ignored during asynchronous mode operations.
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Table 2: BUS OPERATIONS
Asynchronous Mode
BCR[15]=1
Read
Write
Standby
No operation
Configuration register
write
Configuration register
read
DPD
Burst Mode
BCR[15]=0
Async read
Async write
Standby
No operation
Initial burst read
Initial burst write
Burst continue
Configuration register
write
Configuration register
read
DPD
Power
Active
Active
Standby
Idle
Active
Active
Deep
Power-down
Power
Active
Active
Standby
Idle
Active
Active
Active
CLK ADV#
X
X
H or L
X
X
X
L
X
X
X
CE#
L
L
H
L
L
L
H
CE#
L
L
X
X
L
L
H
H
L
L
L
L
OE#
L
X
X
X
H
L
X
OE#
L
X
X
X
X
H
X
WE#
H
L
X
X
L
H
X
WE#
H
L
X
X
H
L
X
CRE
L
L
L
L
H
H
X
CRE
L
L
L
L
L
L
X
UB#/
LB#
L
L
X
X
X
L
X
UB#/
LB#
L
L
X
X
L
X
L
WAIT2
Low-z
High-z
High-z
Low-z
Low-z
Low-z
High-z
WAIT
Low-z
High-z
High-z
Low-z
Low-z
Low-z
Low-z
A/DQ[15:0]
Data out
Data in
High-z
X
High-z
Config.
Reg.out
High-z
A/DQ[15:0]
Data out
Data in
High-z
X
Address
Address
Data out
or
Data in
High-z
Config.
Reg.out
High-z
7
Notes
4, 8
4
5, 6
4, 6
4, 9
4, 9
4, 9
Notes
4
4
5, 6
4, 6
CLK ADV#
H or L
H or L
H or L
H or L
Active
Active
Deep
Power-down
L
L
L
X
L
L
H
H
L
X
L
H
X
H
H
X
X
L
X
Low-z
Low-z
High-z
9, 10
9, 10
7
Note:
1. With burst mode enabled, CLK must be static(HIGH or LOW) during asynchronous READs and asynchronous WRITEs and to achieve standby power
during standby mode.
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are enabled. When only LB# is in select mode, DQ[7:0] are enabled. When only UB# is
in the select mode, DQ[15:8] are enabled.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.
6. VIN = VCCQ or 0V; all device pins must be static (unswitched) in order to achieve standby current.
7. DPD is initiated when CE# transitions from LOW to HIGH after writing RCR[4] to 0. DPD is maintained until CE# transitions from HIGH to LOW.
8.When the BCR is configured for sync mode, sync READ and WRITE, and async READ and WRITE are supported by
Alliance
9. Burst mode operation is initialized through the bus configuration register (BCR[15]).
10. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW for the equivalent of a single-word burst (as indicated
