AS1C512K16PL-70BIN
Revision History
512 Kb x16 Pseudo Static RAM
48ball-FPBGA
Revision Details
Rev 1.0
Preliminary datasheet
Date
Aug.
2018
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
Confidential
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Rev.1.0 Aug. 2018
AS1C512K16PL-70BIN
The
AS1C512K16PL-70BIN
is 8,388,608 bits of Pseudo SRAM which uses DRAM type memory cells,
but this device has refresh-free operation and extreme low power consumption technology. Furthermore
the inter-face is compatible to a low power Asynchronous type SRAM. The
AS1C512K16PL-70BIN
is
organized as 524,288 Words x 16 bit.
GENERAL DESCRIPTION
FEATURES
- Organization :512K x16
-
Address access speed 70ns
- Power Supply Voltage : 1.7 ~ 1.95V
- Separated I/O power(VccQ) & Core power(Vcc)
- Three state outputs
- Byte read/write control by UB# / LB#
- Auto-TCSR for power saving
- Package type : 48-FPBGA 6.0x7.0
- Operating Temperature
.Industrial
(Wireless):
-30
℃
~ 85
℃
PRODUCT FAMILY
Power Dissipation
Part Number
Operating
Temp.
Power Supply
Speed
(t
RC
)
Operating
I
CC
( Max.)
Standby
(I
SB
, Max.)
I
CC1
( f = 1MHz)
I
CC2
( f = f
max
)
AS1C512K16PL-70BIN
-30
℃
to 85
℃
1.7V to 1.95V
70ns
90uA
5mA
25mA
FUNCTION BLOCK DIAGRAM
Self-Refresh
CONTROL
CONTROL
LOGIC
CS#
UB#
LB#
WE#
OE#
COLUMN SELECT
ROW SELECT
A0~A18
ADDRESS
DECODER
Memory Array
512K X 16
DQ0~
DQ15
Din/Dout BUFFER
I/O CIRCUIT
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Rev.1.0 Aug. 2018
AS1C512K16PL-70BIN
PIN DESCRIPTION ( 48-FPBGA-6.00x7.00 )
1
A
LB#
2
OE#
3
A0
4
A1
5
A2
6
NC
B
DQ8
UB#
A3
A4
CS#
DQ0
C
DQ9
DQ10
A5
A6
DQ1
DQ2
D
VSSQ
DQ11
A17
A7
DQ3
VCC
E
VCCQ
DQ12
DNU
A16
DQ4
VSS
F
DQ14
DQ13
A14
A15
DQ5
DQ6
G
H
DQ15
NC
A12
A13
WE#
DQ7
A18
A8
A9
A10
A11
NC
TOP VIEW (Ball Down)
Name
CS#
OE#
WE#
Function
Chip select input
Output enable input
Write enable input
Name
LB#
UB#
VCC
VCCQ
Function
Lower byte (DQ
0~7
)
Upper byte (DQ
8~15
)
Power supply
I/O power supply
DQ
0-15
Data in-out
A
0-18
DNU
Address inputs
Do not use
VSS(Q) Ground
NC
No connection
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Rev.1.0 Aug. 2018
AS1C512K16PL-70BIN
ABSOLUTE MAXIMUM RATINGS
1)
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage Temperature
Operating Temperature
Wireless
Symbol
V
IN
, V
OUT
V
CC
, V
CCQ
P
D
T
STG
T
A
Ratings
-0.2 to V
CCQ
+0.3
-0.2
2)
to 2.5
1.0
-65 to 150
-30 to 85
Unit
V
V
W
o
C
o
C
1. Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device.
Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. Undershoot at power-off : -1.0V in case of pulse width < 20ns
FUNCTIONAL DESCRIPTION
CS#
H
L
L
L
L
L
L
L
L
OE#
X
H
H
L
L
L
X
X
X
WE#
X
H
H
H
H
H
L
L
L
LB#
X
L
X
L
H
L
L
H
L
UB#
X
X
L
H
L
L
H
L
L
DQ
0~7
High-Z
High-Z
High-Z
Data Out
High-Z
Data Out
Data In
High-Z
Data In
DQ
8~15
High-Z
High-Z
High-Z
High-Z
Data Out
Data Out
High-Z
Data In
Data In
Mode
Deselected
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
Lower Byte Write
Upper Byte Write
Word Write
Power
Stand by
Active
Active
Active
Active
Active
Active
Active
Active
Note:
1. X means don’t care. (Must be low or high state)
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Rev.1.0 Aug. 2018
AS1C512K16PL-70BIN
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
V
CC
V
CCQ
V
SS
, V
SSQ
V
IH
V
IL
Min
1.7
1.7
0
V
CCQ
- 0.4
-0.2
2)
Typ
1.8
1.8
0
-
-
Max
1.95
1.95
0
V
CCQ
+ 0.2
1)
0.4
Unit
V
V
V
V
V
1. Overshoot: V
CC
+1.0 V in case of pulse width < 20ns
2. Undershoot: -1.0 V in case of pulse width < 20ns
3. Overshoot and undershoot are sampled, not 100% tested
.
CAPACITANCE
1)
(f =1MHz, T
A
=25
o
C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
8
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Parameter
Input leakage current
Output leakage current
Symbol
I
LI
I
LO
Test Conditions
V
IN
=V
SS
to V
CCQ
, V
CC=
V
CCmax
CS#=V
IH
, OE#=V
IH
or WE#=V
IL
,
V
IO
=V
SS
to V
CCQ
, V
CC=
V
CCmax
Cycle time = 1us, I
IO
=0mA, 100% duty,
Min
-1
-1
Typ
-
-
Max
1
1
Unit
uA
uA
I
CC1
Average operating current
I
CC2
Page access operating
current
Output low voltage
Output high voltage
I
CCP
V
OL
V
OH
CS#<0.2V,
V
IN
<0.2V or V
IN
>V
CCQ
-0.2V
Cycle time = Min, I
IO
=0mA, 100% duty,
CS#=V
IL
, V
IN
=V
IL
or V
IH
tPC = Min,CS#=V
IL
, I
IO
=0mA, Page
add. cycling.
I
OL
= 0.5mA, V
CC=
V
CCmin
I
OH
= -0.5mA, V
CC=
V
CCmin
CS#>V
CCQ
-0.2V, Other inputs = 0 ~ V
CCQ
(Typ. condition : V
CC
=1.8V @ 25
o
C)
(Max. condition : V
CC
=1.95V @ 85
o
C)
-
-
5
mA
-
-
-
0.8*V
CCQ
-
-
-
-
25
15
0.2*V
CCQ
mA
mA
V
V
-
Standby current (CMOS)
I
SB
-
-
90
uA
1. Maximum Icc specifications are tested with V
CC
= V
CCmax.
Confidential
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Rev.1.0 Aug. 2018
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