AS4C1M16F5
®
5V 1M×16 CMOS DRAM (fast-page mode)
Features
• Organization: 1,048,576 words × 16 bits
• High speed
- 50/60 ns
RAS
access time
- 20/25 ns fast page cycle time
- 13/17 ns
CAS
access time
• Low power consumption
- Active:
880 mW max (AS4C1M16E0-60)
- Standby: 11 mW max, CMOS DQ
• Fast page mode
• 1024 refresh cycles, 16 ms refresh interval
-
RAS
-only or
CAS
-before-
RAS
refresh
• Read-modify-write
• TTL-compatible, three-state DQ
• JEDEC standard package and pinout
- 400 mil, 42-pin SOJ
- 400 mil, 44/50-pin TSOP II
• 5V power supply
• Industrial and commercial temperature available
Pin arrangement
SOJ
Vcc
DQ1
DQ2
DQ3
DQ4
Vcc
DQ5
DQ6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
Pin designation
TSOP II
V
SS
DQ16
DQ15
DQ14
DQ13
Pin(s)
V
SS
DQ16
DQ15
DQ14
DQ13
V
SS
DQ12
DQ11
DQ10
DQ9
NC
Description
Address inputs
Row address strobe
Input/output
Output enable
Write enable
Column address strobe, upper byte
Column address strobe, lower byte
Power
Ground
V
SS
DQ12
DQ11
DQ7
DQ8
NC
NC
WE
RAS
NC
NC
A0
A1
DQ10
DQ9
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
V
CC
DQ1
DQ2
DQ
3
DQ4
V
CC
DQ5
DQ6
DQ7
DQ8
NC
1
2
3
4
5
6
7
8
9
10
11
50
49
48
47
46
45
44
43
42
41
40
A0 to A9
RAS
DQ1 to DQ16
OE
WE
UCAS
LCAS
NC
NC
WE
RAS
A2
A3
Vcc
A4
V
SS
NC
NC
A0
A1
A2
A3
V
CC
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
LCAS
UCAS
OE
V
CC
V
SS
A9
A8
A7
A6
A5
A4
V
SS
Selection guide
Symbol
Maximum
RAS
access time
Maximum column address access time
Maximum
CAS
access time
Maximum output enable (
OE
) access time
Minimum read or write cycle time
Minimum fast page mode cycle time
Maximum operating current
Maximum CMOS standby current
t
RAC
t
AA
t
CAC
t
OEA
t
RC
t
PC
I
CC1
I
CC5
AS4C1M16F5-50
50
25
13
13
84
20
170
2.0
AS4C1M16F5-60
60
30
17
15
104
25
160
2.0
Unit
ns
ns
ns
ns
ns
ns
mA
mA
4/11/01; v.0.9.1
Alliance Semiconductor
P. 1 of 21
Copyright © Alliance Semiconductor. All rights reserved.
AS4C1M16F5
®
Functional description
The AS4C1M16F5 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) organized as
1,048,576 words × 16 bits. The AS4C1M16F5 is fabricated using advanced CMOS technology and innovative design
techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The
Alliance 16Mb DRAM family is optimized for use as main memory in personal and portable PCs, workstations, and multimedia
and router switch applications.
The AS4C1M16F5 features high speed page mode operation where read and write operations within a single row (or page)
can be executed at very high speed (15 ns from
XCAS
)by toggling column addresses within that row. Row and column
addresses are alternately latched into input buffers using the falling edge of
RAS
and
xCAS
inputs respectively. Also,
RAS
is used
to make the column address latch transparent, enabling application of column addresses prior to
xCAS
assertion. The
AS4C1M16F5 provides dual
UCAS
and
LCAS
for independent byte control of read and write access.
Refresh on the 1024 address combinations of A0 to A9 must be performed every 16 ms using:
•
RAS
-only refresh:
RAS
is asserted while
xCAS
is held high. Each of the 1024 rows must be strobed. Outputs remain high impedence.
• Hidden refresh:
xCAS
is held low while
RAS
is toggled. Outputs remain low impedence with previous valid data.
•
CAS
-before-
RAS
refresh (CBR): At least one
xCAS
is asserted prior to
RAS
. Refresh address is generated internally.
Outputs are high-impedence (
OE
and
WE
are don't care).
• Normal read or write cycles refresh the row being accessed.
The AS4C1M16F5 is available in the standard 42-pin plastic SOJ and the 44/50-pin TSOP II packages, respectively. It operates
with a single power supply of 5V ± 0.5V. The device provides TTL compatible inputs and outputs.
Logic block diagram
Refresh
controller
V
CC
GND
RAS clock
generator
Column decoder
Sense amp
Data
DQ
buffers
DQ1 to DQ16
RAS
UCAS
LCAS
CAS clock
generator
WE
WE clock
generator
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Address buffers
OE
Row decoder
1024 × 1024 × 16
Array
(16,777,216)
Substrate bias
generator
Recommended operating conditions
Parameter
Supply voltage
Input voltage
Ambient operating temperature
†
Symbol
AS4C1M16F5
AS4C1M16F5
Commercial
Industrial
V
CC
GND
V
IH
V
IL
T
A
Min
4.5
0.0
2.4
–0.5
†
0
-40
Nominal
5.0
0.0
–
–
–
–
Max
5.5
0.0
V
CC
0.8
70
85
Unit
V
V
V
V
°C
V
IL
min -3.0V for pulse widths less than 5 ns.
Recommended operating conditions apply throughout this document unlesss otherwise specified.
4/11/01; v.0.9.1
Alliance Semiconductor
P. 2 of 21
AS4C1M16F5
®
Absolute maximum ratings
Parameter
Input voltage
Input voltage (DQs)
Power supply voltage
Storage temperature (plastic)
Soldering temperature × time
Power dissipation
Short circuit output current
Symbol
V
in
V
DQ
V
CC
T
STG
T
SOLDER
P
D
I
out
Min
-1.0
-1.0
-1.0
-55
–
–
–
Max
+7.0
V
CC
+ 0.5
+7.0
+150
260 × 10
1
50
Unit
V
V
V
°C
o
C × sec
W
mA
DC electrical characteristics
-50
Parameter
Input leakage current
Output leakage current
Operating power
supply current
TTL standby power
supply current
Symbol
I
IL
I
OL
I
CC1
I
CC2
Test conditions
0V
≤
V
in
≤
+5.5V,
Pins not under test = 0V
D
OUT
disabled, 0V
≤
V
out
≤
+5.5V
RAS
,
UCAS
,
LCAS
, Address cycling;
-60
Min
-5
-5
–
–
Max
+5
+5
160
2.5
Unit
µA
µA
mA
mA
1,2
Notes
Min
-5
-5
–
–
Max
+5
+5
170
2.5
t
RC
=min
RAS
=
UCAS
=
LCAS
≥
V
IH
RAS
cycling,
UCAS
=
LCAS
≥
V
IH
,
t
RC
= min of
RAS
low after
XCAS
low.
RAS
= V
IL
,
UCAS
or
LCAS,
Average power supply
current,
RAS
refresh mode I
CC3
or CBR
Fast page mode average
power supply current
CMOS standby power
supply current
Output voltage
CAS
before
RAS
refresh
–
170
–
160
mA
1
I
CC4
I
CC5
V
OH
V
OL
ICC6
address cycling: t
PC
= min
RAS
=
UCAS
=
LCAS
= V
CC
- 0.2V
–
–
2.4
–
–
120
2.0
–
0.4
170
–
–
2.4
–
–
110
2.0
–
0.4
160
mA
mA
V
V
mA
1, 2
I
OUT
= -5.0 mA
I
OUT
= 4.2 mA
RAS
,
UCAS
or
LCAS
cycling, t
RC
= min
current
4/11/01; v.0.9.1
Alliance Semiconductor
P. 3 of 21
AS4C1M16F5
®
AC parameters common to all waveforms
-50
Symbol
t
RC
t
RP
t
RAS
t
CAS
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
t
ASR
t
RAH
t
T
t
REF
t
CP
t
RAL
t
ASC
t
CAH
Parameter
Random read or write cycle time
RAS
precharge time
RAS
pulse width
CAS
pulse width
RAS
to
CAS
delay time
RAS
to column address delay time
CAS
to
RAS
hold time
RAS
to
CAS
hold time
CAS
to
RAS
precharge time
-60
Max
–
–
10K
10K
35
25
–
–
–
–
–
50
16
–
–
–
Min
104
40
60
10
15
12
10
50
5
0
10
1
–
10
30
0
10
Max
–
–
10K
10K
43
30
–
–
–
–
–
50
16
–
–
–
–
Unit Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
4,5
3
6
7
Min
84
30
50
8
15
12
10
40
5
0
8
1
–
8
25
0
8
Row address setup time
Row address hold time
Transition time (rise and fall)
Refresh period
CAS precharge time
Column address to
RAS
lead time
Column address setup time
Column address hold time
Read cycle
-50
Symbol
t
RAC
t
CAC
t
AA
t
RCS
t
RCH
tRRH
-60
Max
50
13
25
–
–
–
Min
–
–
–
0
0
0
Max
60
17
30
–
–
–
Unit Notes
ns
ns
ns
ns
ns
ns
9
9
6
6,13
7,13
Parameter
Access time from
RAS
Access time from
CAS
Access time from address
Read command setup time
Read command hold time to
CAS
Read command hold time to
RAS
Min
–
–
–
0
0
0
4/11/01; v.0.9.1
Alliance Semiconductor
P. 4 of 21
AS4C1M16F5
®
Write cycle
-50
Symbol
t
WCS
t
WCH
t
WP
t
RWL
t
CWL
t
DS
t
DH
Parameter
Write command setup time
Write command hold time
Write command pulse width
Write command to
RAS
lead time
Write command to
CAS
lead time
Data-in setup time
Data-in hold time
Min
0
10
10
10
8
0
8
Max
–
–
–
–
–
–
–
Min
0
10
10
10
10
0
10
-60
Max
–
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
12
12
Notes
11
11
Read-modify-write cycle
-50
Symbol
t
RWC
t
RWD
t
CWD
t
AWD
Parameter
Read-write cycle time
RAS
to
WE
delay time
CAS
to
WE
delay time
-60
Max
–
–
–
–
Min
135
77
35
47
Max
–
–
–
–
Unit
ns
ns
ns
ns
11
11
11
Notes
Min
113
67
32
42
Column address to
WE
delay time
Refresh cycle
-50
Symbol
t
CSR
t
CHR
t
RPC
t
CPT
Parameter
CAS
setup time (
CAS
-before-
RAS
)
CAS
hold time (
CAS
-before-RAS)
-60
Max
–
–
–
Min
5
10
0
10
Max
–
–
–
–
Unit
ns
ns
ns
ns
Notes
3
3
Min
5
8
0
10
RAS precharge to
CAS
hold time
CAS
precharge time
(CBR counter test)
4/11/01; v.0.9.1
Alliance Semiconductor
P. 5 of 21
