128k x 8 BIT SUPER LOW POWER CMOS SRAM
AS6C1008L
Revision History
128k x 8 BIT AS6C1008L
Revision
Rev 1.a
Rev 2.a
Details
Preliminary datasheet
Delete -35ns speed grade information
Date
Oct 2007
Apr 2016
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
Confidential
- 1/15 -
Rev.2.a April 2016
128k x 8 BIT SUPER LOW POWER CMOS SRAM
FEATURES
Fast access time : 55ns
Low power consumption:
Operating current : 10mA (TYP.)
Standby current : 1µA (TYP.)
Single 2.7V ~ 5.5V power supply
All outputs TTL compatible
Fully static operation
Tri-state output
Data retention voltage : 1.5V (MIN.)
Lead freeandgreenpackageavailable
Package : 32-pin 450 mil SOP
32-pin 600 mil P-DIP
32-pin 8mm x 20mm TSOP-I
32-pin 8mm x 13.4mm STSOP
36-ball 6mm x 8mm TFBGA
AS6C1008L
GENERAL DESCRIPTION
The AS6C1008L is a 1,048,576-bit low power
CMOS static random access memory organized as
131,072 words by 8 bits. It is fabricated using very
high performance, high reliability CMOS technology.
Its standby current is stable within the range of
operating temperature.
The AS6C1008L is well designed for very low power
system applications, and particularly well suited for
battery back-up nonvolatile memory application.
The AS6C1008-55 operates from a single power
supply of 2.7V ~ 5.5V and all inputs and outputs are
fully TTL compatible
PRODUCT FAMILY
Product Family
AS6C1008L
Operating Temperature
-40 ~ 85℃
Vcc Range
2.7 ~ 5.5V
Speed
55ns
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
SYMBOL
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
Vcc
Vss
A0 - A16
DQ0 – DQ7
DECODER
128Kx8
MEMORY ARRAY
CE#, CE2
WE#
OE#
V
CC
V
SS
NC
A0-A16
DQ0-DQ7
I/O DATA
CIRCUIT
COLUMN I/O
CE#
CE2
WE#
OE#
CONTROL
CIRCUIT
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128k x 8 BIT SUPER LOW POWER CMOS SRAM
PIN CONFIGURATION
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
1
2
3
4
5
32
31
30
29
28
Vcc
A15
CE2
WE#
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A11
A9
A8
A13
WE#
CE2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
A3
AS6C1008L
AS6C1008
SOP/P-DIP
6
7
8
9
10
11
12
13
14
15
16
27
26
25
24
23
22
21
20
19
18
17
AS6C1008
TSOP-I/STSOP
A
B
C
D
E
F
G
H
A0
DQ4
DQ5
Vss
Vcc
DQ6
A1
A2
CE2
WE#
NC
A3
A4
A5
A6
A7
A8
DQ0
DQ1
Vcc
Vss
NC
CE#
A11
NC
A16
A12
A15
A13
DQ2
DQ3
A14
DQ7 OE#
A9
A10
1
2
3
4
TFBGA
5
6
ABSOLUTE MAXIMUM
RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Operating Temperature
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
SYMBOL
V
TERM
T
A
T
STG
P
D
I
OUT
T
SOLDER
RATING
-0.5 to 7.0
-40 to 85(I grade)
-65 to 150
1
50
260
UNIT
V
℃
℃
W
mA
℃
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Rev.2.a April 2016
128k x 8 BIT SUPER LOW POWER CMOS SRAM
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
AS6C1008L
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
CE#
H
X
L
L
L
CE2
X
L
H
H
H
OE#
X
X
H
L
X
WE#
X
X
H
H
L
I/O OPERATION
High-Z
High-Z
High-Z
D
OUT
D
IN
SUPPLY CURRENT
I
SB1
I
SB1
I
CC
,I
CC1
I
CC
,I
CC1
I
CC
,I
CC1
H = V
IH
, L = V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITION
MIN.
PARAMETER
Supply Voltage
V
CC
2.7
*1
Input High Voltage
V
IH
0.7*Vcc
*2
Input Low Voltage
V
IL
- 0.2
V
CC
≧
V
IN
≧
V
SS
Input Leakage Current
I
LI
-1
Output Leakage
V
CC
≧
V
OUT
≧
V
SS,
-1
I
LO
Output Disabled
Current
Output High Voltage
V
OH
I
OH
= -1mA
2.2
Output Low Voltage
V
OL
I
OL
= 2mA
-
Cycle time = Min.
CE# = V
IL
and CE2 = V
IH
,
I
CC
-
I
I/O
= 0mA
Average Operating
Cycle time = 1µs
Power supply Current
CE#
≦
0.2V and CE2
≧
V
CC
-0.2V,
I
CC1
-
I
I/O
= 0mA
other pins at 0.2V or V
CC
-0.2V
CE#
≧
V
CC
-0.2V
-
-SL
or CE2
≦
0.2V
Standby Power
I
SB1
Other pins at 0.2V
Supply Current
-SLE/-SLI
-
or Vcc-0.2V
Notes:
1. V
IH
(max) = V
CC
+ 3.0V for pulse width less than 10ns.
2. V
IL
(min) = V
SS
- 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at V
CC
= V
CC
(TYP.) and T
A
= 25℃
TYP.
3.0
-
-
-
-
2.7
-
10
*4
MAX.
5.5
V
CC
+0.3
0.6
1
1
-
0.4
60
UNIT
V
V
V
µA
µA
V
V
mA
1
10
mA
1
1
10
10
µA
µA
Confidential
- 4/15 -
Rev.2.a April 2016
128k x 8 BIT SUPER LOW POWER CMOS SRAM
CAPACITANCE
(T
A
= 25 C, f = 1.0MHz)
O
AS6C1008L
MAX
6
8
UNIT
pF
pF
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to V
CC
- 0.2V
3ns
1.5V
C
L
= 50pF + 1TTL, I
OH
/I
OL
= -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
SYM.
t
RC
t
AA
t
ACE
t
OE
t
CLZ
*
t
OLZ
*
t
CHZ
*
t
OHZ
*
t
OH
AS6C1008L
MIN.
MAX.
35
-
-
35
-
35
-
25
10
-
5
-
-
15
-
15
10
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM.
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
*
t
WHZ
*
AS6C1008L
MIN.
MAX.
35
-
30
-
30
-
0
-
25
-
0
-
20
-
0
-
5
-
-
15
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*These parameters are guaranteed by device characterization, but not production tested.
Confidential
- 5/15 -
Rev.2.a April 2016
