The AS6YB51216 is a low-power CMOS 8,388,608-bit Static Random Access Memory (SRAM) device organized as 524,288
words x 16 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 70/85 ns are ideal for low-power applications. Active high and low chip
enables (CS1 and CS2) permit easy memory expansion with multiple-bank memory systems.
When CS1 is high or CS2 is low, or UB and LB are high, the device enters standby mode. The AS6YB51216 is guaranteed not to
exceed 33
µ
W at 2.2V. The device also retains data when V
CC
is reduced to 1.0V for even lower power consumption.
The device can also be put into standby mode when deselected (CS1 is high or CS2 is low). The input/output pins (I/O0
through I/O15) are placed in a high-impedance state when deselected ( CS1 is high or CS2 is low), outputs are disabled (OE
High), UB and LB are disabled (UB, LB High), or during a write operation ( CS1 is low or CS2 is high and WE Low).
Writing to the device is accomplished by taking Chip Enables CS1 Low, CS2 High and Write Enable (WE) input Low. If Byte Low
Enable (LB) is Low, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0
through A18). If Byte High Enable (UB) is Low, then data from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A18). To avoid bus contention, external devices should drive I/O pins only after out-
puts have been disabled with output enable (OE) or write enable (WE).
Reading from the device is accomplished by taking Chip Enable CS1 Low, CS2 High and Output Enable (OE) Low while forcing
the Write Enable (WE) High. If Byte Low Enable (LB) is Low, then data from the memory location specified by the address pins
will appear on I/O0 to I/O7. If Byte High Enable (UB) is Low, then data from memory will appear on I/O8 to I/O15.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 1.65V to 2.2V supply. Device is available in the
JEDEC 48-ball FBGA packages.
Absolute maximum ratings
Parameter
Voltage on V
CC
relative to V
SS
Voltage on any I/O pin relative to GND
Power dissipation
Storage temperature (plastic)
Temperature with V
CC
applied
DC output current (low)
Symbol
V
tIN
V
tI/O
P
D
T
stg
T
bias
I
OUT
Min
–0.5
–0.5
–
–65
–55
–
1.0
+150
+125
20
Max
V
CC
+ 0.5
Unit
V
V
W
°
C
°
C
mA
Note: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional opera-
tion of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
11/1/01; V.0.9.8
Alliance Semiconductor
P. 2 of 11
AS6YB51216
Truth table
CS1
H
X
X
L
L
L
CS2
X
L
X
H
H
H
WE
X
X
X
H
H
H
OE
X
X
X
H
H
L
LB
X
X
H
L
X
L
H
L
L
L
H
L
X
H
L
UB
X
X
H
X
L
H
L
L
H
L
L
I
CC
I
CC
I
CC
High Z
D
OUT
High Z
D
OUT
D
IN
High Z
D
IN
High Z
High Z
D
OUT
D
OUT
High Z
D
IN
D
IN
Write (I
CC
)
Read (I
CC
)
Output disable (I
CC
)
I
SB
High Z
High Z
Standby (I
SB
)
Supply
Current
I/O1–I/O8 I/O9–I/O16
Mode
Key: X = Don’t care, L = Low, H = High.Recommended operating condition (over the operating range)
DC Recommended operating condition (over the operating range)
