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April 2005

AS7C3364NTF32B

AS7C3364NTF36B

3.3V 64K × 32/36 Flowthrough Synchronous SRAM with NTD

Features

•

Organization: 65,536 words × 32 or 36 bits

NTD

™

architecture for efficient bus operation

Fast clock to data access: 7.5/8.0/10.0 ns

Fast OE access time: 3.5/4.0 ns

Fully synchronous operation

Flow-through mode

Asynchronous output enable control

Available in 100-pin TQFP package

Byte write enables

Clock enable for operation hold

•

Multiple chip enables for easy expansion

3.3V core power supply

2.5V or 3.3V I/O operation with separate V

DDQ

Self-timed write cycles

Interleaved or linear burst modes

Snooze mode for standby operation

Logic block diagram

A[15:0]

Address

Burst logic

CLK

CE0

CE1

CE2

R/W

BWa

BWb

BWc

BWd

ADV / LD

LBO

Write delay

addr. registers

CLK

Control

logic

CLK

Write Buffer

CLK

64K x 32/36

SRAM

Array

DQ[a,b,c,d]

32/36

Data

Input

CLK

32/36

CLK

CEN

Output

Buffer

32/36

DQ[a,b,c,d]

Selection guide

-75

Minimum cycle time

Maximum clock access time

Maximum operating current

Maximum standby current

Maximum CMOS standby current (DC)

8.5

7.5

260

110

-80

8.0

230

100

-10

200

Units

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AS7C3364NTF32B/36B

2 Mb Synchronous SRAM products list

1,2

Org

128KX18

64KX32

64KX36

128KX18

64KX32

64KX36

128KX18

64KX32

64KX36

128KX18

64KX32

64KX36

128KX18

64KX32

64KX36

Part Number

AS7C33128PFS18B

AS7C3364PFS32B

AS7C3364PFS36B

AS7C33128PFD18B

AS7C3364PFD32B

AS7C3364PFD36B

AS7C33128FT18B

AS7C3364FT32B

AS7C3364FT36B

AS7C33128NTD18B

AS7C3364NTD32B

AS7C3364NTD36B

AS7C33128NTF18B

AS7C3364NTF32B

AS7C3364NTF36B

Mode

PL-SCD

PL-DCD

NTD-PL

NTD-FT

Speed3

200/166/133 MHz

6.5/7.5/8.0/10 ns

200/166/133 MHz

7.5/8.0/10 ns

1 Core Power Supply: VDD = 3.3V + 0.165V

2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O

VDDQ = 2.5V + 0.125V for 2.5V I/O

3 Refer corresponding product datasheets for the latest information on Clock Speed and Clock Access Time availability.

PL-SCD

PL-DCD

NTD

-PL

NTD-FT

Pipelined Burst Synchronous SRAM - Single Cycle Deselect

Pipelined Burst Synchronous SRAM - Double Cycle Deselect

Flow-through Burst Synchronous SRAM

Pipelined Burst Synchronous SRAM with NTD

Flow-through Burst Synchronous SRAM with NTD

1. NTD: No Turnaround Delay. NTD

is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property

of their respective owners.

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AS7C3364NTF32B/36B

100-pin TQFP - top view

CE0

CE1

BWd

BWc

BWb

BWa

CE2

CLK

R/W

CEN

ADV/LD

100

NC/DQPc

DQc0

DQc1

DDQ

SSQ

DQc2

DQc3

DQc4

DQc5

SSQ

DDQ

DQc6

DQc7

DQd0

DQd1

DDQ

SSQ

DQd2

DQd3

DQd4

DQd5

SSQ

DDQ

DQd6

DQd7

NC/DQPd

TQFP 14 x 20mm

DQPb/NC

DQb7

DQb6

DDQ

SSQ

DQb5

DQb4

DQb3

DQb2

SSQ

DDQ

DQb1

DQb0

DQa7

DQa6

DDQ

SSQ

DQa5

DQa4

DQa3

DQa2

SSQ

DDQ

DQa1

DQa0

DQPa/NC

Note: For pins 1, 30, 51, and 80, NC applies to the x32 configuration. DQPn applies to the x36 configuration.

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AS7C3364NTF32B/36B

Functional Description

The AS7C3364NTF32B/36B family is a high performance CMOS 2 Mbit synchronous Static Random Access Memory

(SRAM) organized as 65,536 words × 32 or 36 bits and incorporates a LATE Write.

This variation of the 2Mb+ synchronous SRAM uses the No Turnaround Delay (NTD

™

) architecture, featuring an enhanced

write operation that improves bandwidth over flowthrough burst devices. In a normal flowthrough burst device, the write data,

command, and address are all applied to the device on the same clock edge. If a read command follows this write command,

the system must wait for one dead cycle for valid data to become available. This dead cycle can significantly reduce overall

bandwidth for applications requiring random access or read-modify-write operations.

NTD

™

devices use the memory bus more efficiently by introducing a write latency which matches the one-cycle flow-

through read latency. Write data is applied one cycle after the write command and address, allowing the read pipeline to clear.

With NTD

™

, write and read operations can be used in any order without producing dead bus cycles.

Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 36

bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied

to the device one clock cycle later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write

operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-selected by

any of the three chip enable inputs.

Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip

select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any

device operations, including burst, can be stalled using the CEN=1, the clock enable input.

The AS7C3364NTF32B/36B operates with a 3.3V ± 5% power supply for the device core (V

). DQ circuits use a separate

power supply (V

DDQ

) that operates across 2.5V or 3.3V ranges. These devices are available in a 100-pin TQFP package.

TQFP Capacitance

Parameter

Input capacitance

I/O capacitance

*Guranteed not tested

Symbol

IN*

I/O*

Test conditions

= 0V

= V

out

= 0V

Min

Max

Unit

TQFP thermal resistance

Description

Thermal resistance

(junction to ambient)

Thermal resistance

(junction to top of case)

1 This parameter is sampled

Conditions

1–layer

Test conditions follow standard test methods and

procedures for measuring thermal impedance,

per EIA/JESD51

4–layer

Symbol

Typical

Units

°C/W

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AS7C3364NTF32B/36B

Signal descriptions

Signal

CLK

CEN

A, A0, A1

DQ[a,b,c,d]

CE0, CE1,

CE2

ADV/LD

R/W

BW[a,b,c,d]

LBO

I/O Properties

I/O

CLOCK

SYNC

ASYNC

STATIC

ASYNC

Description

Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.

Clock enable. When de-asserted high, the clock input signal is masked.

Address. Sampled when all chip enables are active and ADV/LD is asserted.

Data. Driven as output when the chip is enabled and OE is active.

Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.

Are ignored when ADV/LD is high.

Advance or Load. When sampled high, the internal burst address counter will increment in

the order defined by the LBO input value. When low, a new address is loaded.

A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE

operation. Is ignored when ADV/LD is high.

Byte write enables. Used to control write on individual bytes. Sampled along with WRITE

command and BURST WRITE.

Asynchronous output enable. I/O pins are not driven when OE is inactive.

Selects Burst mode. When tied to V

or left floating, device follows interleaved Burst order. When

driven Low, device follows linear Burst order.

This signal is internally pulled High.

Snooze. Places device in low power mode; data is retained. Connect to GND if unused.

No connect

Snooze Mode

SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I

SB2

. The duration of

SNOOZE MODE is dictated by the length of time the ZZ is in a High state.

The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.

When the ZZ pin becomes a logic High, I

SB2

is guaranteed after the time t

ZZI

is met. After entering SNOOZE MODE, all inputs except ZZ

is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.

Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting

SNOOZE MODE during t

PUS

, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.

Burst order

Interleaved burst order LBO = 1

A1 A0

Starting address

First increment

Second increment

Third increment

0 0

0 1

1 0

1 1

A1 A0

0 1

0 0

1 1

1 0

A1 A0

1 0

1 1

0 0

0 1

A1 A0

1 1

1 0

0 1

Starting Address

First increment

Second increment

Third increment

Linear burst order LBO = 0

A1 A0

0 0

0 1

1 0

1 1

A1 A0

0 1

1 0

1 1

0 0

A1 A0

1 0

1 1

0 0

0 1

A1 A0

1 1

0 0

0 1

1 0

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参数对比

与AS7C3364NTF36B-80TQI相近的元器件有：AS7C3364NTF32B-75TQC、AS7C3364NTF32B-75TQI、AS7C3364NTF32B-80TQC、AS7C3364NTF32B-80TQI、AS7C3364NTF36B-10TQI、AS7C3364NTF36B-75TQC、AS7C3364NTF36B-75TQI、AS7C3364NTF36B-80TQC、AS7C3364NTF32B-10TQC。描述及对比如下：

型号	AS7C3364NTF36B-80TQI	AS7C3364NTF32B-75TQC	AS7C3364NTF32B-75TQI	AS7C3364NTF32B-80TQC	AS7C3364NTF32B-80TQI	AS7C3364NTF36B-10TQI	AS7C3364NTF36B-75TQC	AS7C3364NTF36B-75TQI	AS7C3364NTF36B-80TQC	AS7C3364NTF32B-10TQC
描述	ZBT SRAM, 64KX36, 8ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100	ZBT SRAM, 64KX32, 7.5ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100	ZBT SRAM, 64KX32, 7.5ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100	ZBT SRAM, 64KX32, 8ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100	ZBT SRAM, 64KX32, 8ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100	ZBT SRAM, 64KX36, 10ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100	ZBT SRAM, 64KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100	ZBT SRAM, 64KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100	ZBT SRAM, 64KX36, 8ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100	ZBT SRAM, 64KX32, 10ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合
厂商名称	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]
零件包装代码	QFP	QFP	QFP	QFP	QFP	QFP	QFP	QFP	QFP	QFP
包装说明	LQFP,	LQFP,	LQFP,	LQFP,	LQFP,	LQFP,	LQFP,	LQFP,	LQFP,	LQFP,
针数	100	100	100	100	100	100	100	100	100	100
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN代码	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
最长访问时间	8 ns	7.5 ns	7.5 ns	8 ns	8 ns	10 ns	7.5 ns	7.5 ns	8 ns	10 ns
其他特性	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE
JESD-30 代码	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100
JESD-609代码	e0	e0	e0	e0	e0	e0	e0	e0	e0	e0
长度	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm
内存密度	2359296 bit	2097152 bit	2097152 bit	2097152 bit	2097152 bit	2359296 bit	2359296 bit	2359296 bit	2359296 bit	2097152 bit
内存集成电路类型	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM
内存宽度	36	32	32	32	32	36	36	36	36	32
功能数量	1	1	1	1	1	1	1	1	1	1
端子数量	100	100	100	100	100	100	100	100	100	100
字数	65536 words	65536 words	65536 words	65536 words	65536 words	65536 words	65536 words	65536 words	65536 words	65536 words
字数代码	64000	64000	64000	64000	64000	64000	64000	64000	64000	64000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	85 °C	70 °C	85 °C	70 °C	85 °C	85 °C	70 °C	85 °C	70 °C	70 °C
组织	64KX36	64KX32	64KX32	64KX32	64KX32	64KX36	64KX36	64KX36	64KX36	64KX32
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LQFP	LQFP	LQFP	LQFP	LQFP	LQFP	LQFP	LQFP	LQFP	LQFP
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm
最大供电电压 (Vsup)	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V
最小供电电压 (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL
端子面层	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm
端子位置	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
宽度	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
Base Number Matches	1	1	1	1	1	1	1	1	1	1