ASM5P2305A, ASM5P2309A
3.3 V Zero Delay Buffer
Description
ASM5P2309A is a versatile, 3.3 V zero−delay buffer designed to
distribute high−speed clocks. It accepts one reference input and drives
out nine low−skew clocks. It is available in a 16−pin package. The
ASM5P2305A is the eight−pin version of the ASM5P2309A. It
accepts one reference input and drives out five low−skew clocks.
The
−1H
version of the ASM5P230xA operates at up to 133 MHz
frequencies, and has higher drive than the
−1
devices. All parts have
on−chip PLLs that lock to an input clock on the REF. The PLL
feedback is on−chip and is obtained from the CLKOUT.
ASM5P2309A has two banks of four outputs each, which can be
controlled by the Select inputs as shown in the
Select Input Decoding
Table.
The select input also allows the input clock to be directly
applied to the outputs for chip and system testing purposes.
Multiple ASM5P2309A and ASM5P2305A devices can accept the
same input clock and distribute it. In this case the skew between the
outputs of the two devices is guaranteed to be less than 700 pS.
All outputs have less than 200 pS of cycle−to−cycle jitter. The input
and output propagation delay is guaranteed to be less than
±350
pS,
and the output to output skew is guaranteed to be less than 200 pS.
The ASM5P2309A and the ASM5P2305A are available in two
different configurations, as shown in the ordering information table.
The ASM5P2305A−1 / ASM5P2309A−1 is the base part. The
ASM5P2305A−1H / ASM5P2309A−1H is the high drive version of
the
−1
and its rise and fall times are faster than
−1
part.
Features
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SOIC−8
S SUFFIX
CASE 751BD
TSSOP−8
T SUFFIX
CASE 948AL
SOIC−16
S SUFFIX
CASE 751BG
TSSOP−16
T SUFFIX
CASE 948AN
PIN CONFIGURATIONS
REF
CLK
CLK1
GND
ASM5P2305A
(Top View)
CLKOUT
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
ASM5P2309A
(Top View)
1
CLKOUT
CLK4
V
DD
CLK3
•
10 MHz to 133 MHz Operating Range, Compatible with CPU and
•
•
•
•
•
•
•
•
•
PCI Bus Frequencies
Zero Input−output Propagation Delay
Multiple Low−skew Outputs
♦
Output−output Skew less than 200 pS
♦
Device−device Skew less than 700 pS
♦
One Input Drives 9 Outputs, Grouped as
4 + 4 + 1 (ASM5P2309A)
♦
One Input Drives 5 Outputs (ASM5P2305A)
Less than 200 pS Cycle−to−Cycle Jitter is Compatible with Pentium
®
Based Systems
Test Mode to Bypass PLL (ASM5P2309A Only, Refer to
Select Input
Decoding Table)
Packaging Information:
ASM5P2309A: 16−pin SOIC, TSSOP
ASM5P2305A: 8−pin SOIC, TSSOP
Commercial and Industrial Temperature Range
3.3 V Operation
Advanced 0.35
m
CMOS Technology
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
1
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
©
Semiconductor Components Industries, LLC, 2011
August, 2011
−
Rev. 4
1
Publication Order Number:
ASM5P2305A/D
ASM5P2305A, ASM5P2309A
PLL
REF
ASM5P2309A
MUX
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
REF
PLL
CLKOUT
CLK1
ASM5P2305A
CLK2
CLK3
CLK4
S2
S1
Select
Input
Decoding
CLKB1
CLKB2
CLKB3
CLKB4
Figure 1. Block Diagram
Table 1. SELECT INPUT DECODING FOR ASM5P2309A
S2
0
0
1
1
S1
0
1
0
1
Clock A1
−
A4
Three−state
Driven
Driven
Driven
Clock B1
−
B4
Three−state
Three−state
Driven
Driven
CLKOUT
(Note 1)
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shut−Down
N
N
Y
N
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the
reference and the output.
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the CLKOUT pin is
the internal feedback to the PLL, its relative loading can
adjust the input−output delay.
1500
For applications requiring zero input−output delay, all
outputs, including CLKOUT, must be equally loaded. Even
if CLKOUT is not used, it must have a capacitive load equal
to that on other outputs, for obtaining zero input−output
delay.
REF−Input to CLKA / CLKB Delay (pS)
1000
500
0
−30 −25
−500
−20
−15
−10
−5
0
5
10
15
20
25
30
−1000
−1500
Figure 2. Output Load Difference: CLKOUT Load
−
CLKA/CLKB Load (pF)
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ASM5P2305A, ASM5P2309A
Table 2. PIN DESCRIPTION FOR ASM5P2305A
Pin #
1
2
3
4
5
6
7
8
Pin Name
REF (Note 2)
CLK2 (Note 3)
CLK1 (Note 3)
GND
CLK3 (Note 3)
V
DD
CLK4 (Note 3)
CLKOUT (Note 3)
Description
Input reference clock frequency, 5 V−tolerant input
Buffered clock output
Buffered clock output
Ground
Buffered clock output
3.3 V supply
Buffered clock output
Buffered clock output, internal feedback on this pin
Table 3. PIN DESCRIPTION FOR ASM5P2309A
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
REF (Note 2)
CLKA1 (Note 3)
CLKA2 (Note 3)
V
DD
GND
CLKB1 (Note 3)
CLKB2 (Note 3)
S2 (Note 4)
S1 (Note 4)
CLKB3 (Note 3)
CLKB4 (Note 3)
GND
V
DD
CLKA3 (Note 3)
CLKA4 (Note 3)
CLKOUT (Note 3)
Description
Input reference clock frequency, 5 V tolerant input
Buffered clock output, bank A
Buffered clock output, bank A
3.3 V supply
Ground
Buffered clock output, bank B
Buffered clock output, bank B
Select input, bit 2
Select input, bit 1
Buffered clock output, bank B
Buffered clock output, bank B
Ground
3.3 V supply
Buffered clock output, bank A
Buffered clock output, bank A
Buffered output, internal feedback on this pin
2. Weak pull−down.
3. Weak pull−down on all outputs.
4. Weak pull−up on these inputs.
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ASM5P2305A, ASM5P2309A
Table 4. ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
Storage Temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22− A114−B)
Min
−0.5
−0.5
−0.5
−65
Max
+4.6
V
DD
+ 0.5
7
+150
260
150
2000
Unit
V
V
V
°C
°C
°C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. OPERATING CONDITIONS
(for ASM5P2305A (−1,
−1H)
and ASM5P2309A (−1,
−1H))
Parameter
V
DD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature
(Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
Commercial temperature
Industrial temperature
Description
Min
3.0
0
−40
Max
3.6
70
85
30
10
7
pF
pF
pF
Unit
V
°C
Table 6. ELECTRICAL CHARACTERISTICS
(for ASM5P2305A (−1,
−1H)
and ASM5P2309A (−1,
−1H))
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Description
Input LOW Voltage (Note 5)
Input HIGH Voltage (Note 5)
Input LOW Current
Input HIGH Current
Output LOW Voltage (Note 6)
Output HIGH Voltage (Note 6)
Supply
Current
Commercial temp.
Industrial temp.
V
IN
= 0 V
V
IN
= V
DD
I
OL
= 8 mA (−1)
I
OL
= 12 mA (−1H)
I
OH
=
−8
mA (−1)
I
OH
=
−12
mA (−1H)
Unloaded outputs at 66.67 MHz,
SEL inputs at V
DD
2.4
30
32
2.2
50
100
0.4
Test Conditions
Min
Typ
Max
0.8
Unit
V
V
mA
mA
V
V
mA
5. REF input has a threshold voltage of V
DD
/2.
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ASM5P2305A, ASM5P2309A
Table 7. SWITCHING CHARACTERISTICS
(for ASM5P2305A (−1,
−1H)
and ASM5P2309A (−1,
−1H)
(Notes 7, 8)
Parameter
Output Frequency
Duty Cycle (Note 9)
Test Conditions
30 pF load
10 pF load
Measured at 1.4 V, F
OUT
> 50 MHz
Measured at V
DD
/2, F
OUT
≤
50 MHz
Output Rise Time (Note 9)
Measured between 0.8 V and 2.0 V
(−1)
(−1H)
Output Fall Time (Note 9)
Measured between 2.0 V and 0.8 V
(−1)
(−1H)
Output−to−output skew (Note 9)
Delay, REF Rising Edge to
CLKOUT Rising Edge (Note 9)
Device−to−Device Skew (Note 9)
Cycle−to−cycle Jitter (Note 9)
PLL Lock Time (Note 9)
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the CLKOUT pins of the device
Measured at 66.67 MHz, loaded outputs
Stable power supply, valid clock presented on REF pin
0
0
1.5
1.5
Min
10
10
40
45
50
50
Typ
Max
100
133
60
55
2.25
2
2.25
2
200
±350
700
200
1.0
pS
pS
pS
pS
mS
nS
nS
Unit
MHz
%
7. For all measurements use Test Circuit #1.
8. All parameters are specified with loaded outputs.
9. Parameter is guaranteed by design and characterization. Not 100% tested in production.
TEST CIRCUIT #1
22
W
+3.3 V
V
DD
0.1
mF
ASM5P2305A
ASM5P2309A
GND
CLK OUT
C
LOAD
22
W
CLK A / CLK B
C
LOAD
Figure 3. Test Circuit
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