Features
•
Low-voltage and Standard-voltage Operation
•
•
•
•
•
•
•
•
•
•
•
•
– 2.7 (V
CC
= 2.7 to 5.5V)
– 1.8 (V
CC
= 1.8 to 5.5V)
Low-power Devices (I
SB
= 6 µA at 5.5V) Available
Internally Organized 8192 x 8
2-Wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bi-directional Data Transfer Protocol
400 kHz Clock Rate
Write Protect Pin for Hardware Data Protection
32-Byte Page Write Mode (Partial Page Writes Allowed)
Self-Timed Write Cycle (5 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
Lead-free/Halogen-free Devices Available
8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP Packages
2-Wire
Serial EEPROM
64K (8192 x 8)
Description
The AT24C64B provides 65,536 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 8192 words of 8 bits each. The device’s
cascadable feature allows up to 8 devices to share a common 2-wire bus. The device
is optimized for use in many industrial and commercial applications where low power
and low voltage operation are essential. The AT24C64B is available in space saving
8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP packages and is accessed via a
2-wire serial interface. In addition, the entire family is available in 2.7V (2.7 to 5.5V)
and 1.8V (1.8 to 5.5V) versions.
AT24C64B
Pin Configurations
Pin Name
A0 - A2
SDA
SCL
WP
Function
Address Inputs
Serial Data
Serial Clock Input
Write Protect
8-lead PDIP
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
A0
A1
A2
GND
8-lead SOIC
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
2-Wire, 32K
Serial E
2
PROM
8-lead TSSOP
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
3350C–SEEPR–5/04
1
AT24C64B
Absolute Maximum Ratings*
Operating Temperature...................................... -55 to +125°C
Storage Temperature ......................................... -65 to +150°C
Voltage on Any Pin
with Respect to Ground ....................................... -1.0 to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Block Diagram
2
3350C–SEEPR–5/04
AT24C64B
Pin Description
SERIAL CLOCK (SCL):
The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA):
The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/ADDRESSES (A2, A1, A0):
The A2, A1 and A0 pins are device address inputs
that are hard wired or left not connected for hardware compatibility with other AT24CXX
devices. When the pins are hardwired, as many as eight 64K devices may be addressed
on a single bus system (device addressing is discussed in detail under the Device
Addressing section). If the pins are left floating, the A2, A1 and A0 pins will be internally
pulled down to GND if the capacitive coupling to the circuit board V
CC
plane is <3pF.
If coupling is >3pF, Atmel recommends connecting the address pins to GND.
WRITE PROTECT (WP):
The write protect input, when connected to GND, allows nor-
mal write operations. When WP is connected high to V
CC
, all write operations to the
upper quandrant (16K bits) of memory are inhibited. If the pin is left floating, the WP pin
will be internally pulled down to GND if the capacitive coupling to the circuit board V
CC
plane is <3pF. If coupling is >3pF, Atmel recommends connecting the pin to GND.
Memory Organization
AT24C64B, 64K SERIAL EEPROM:
The 64K is internally organized as 256 pages of
32 bytes each. Random word addressing requires a 13 bit data word address.
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3350C–SEEPR–5/04
AT24C64B
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25°C, f = 1.0 MHz, V
CC
= +1.8V.
Symbol
C
I/O
C
IN
Note:
Test Condition
Input/Output Capacitance (SDA)
Input Capacitance (A
0
, A
1
, A
2
, SCL)
1. This parameter is characterized and is not 100% tested.
Max
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
DC Characteristics
Applicable over recommended operating range from: T
AI
= -40 to +85°C, V
CC
= +1.8 to +5.5V (unless otherwise noted).
Symbol
V
CC1
V
CC2
V
CC3
I
CC1
I
CC2
I
SB1
I
SB2
I
SB3
I
LI
I
LO
V
IL
V
IH
V
OL2
V
OL1
Note:
Parameter
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current
Supply Current
Standby Current
(1.8V option)
Standby Current
(2.7V option)
Standby Current
(5V option)
Input Leakage
Current
Output Leakage
Current
Input Low Level
(1)
Input High Level
(1)
Output Low Level
Output Low Level
V
CC
= 3.0V
V
CC
= 1.8V
I
OL
= 2.1 mA
I
OL
= 0.15 mA
V
CC
= 5.0V
V
CC
= 5.0V
V
CC
= 1.8V
V
CC
= 2.7V
V
CC
= 4.5 - 5.5V
V
IN
= V
CC
or V
SS
V
OUT
= V
CC
or V
SS
-0.6
V
CC
x 0.7
READ at 400 kHz
WRITE at 400 kHz
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
0.10
0.05
Test Condition
Min
1.8
2.7
4.5
0.4
2.0
Typ
Max
5.5
5.5
5.5
1.0
3.0
1.0
2.0
6.0
3.0
3.0
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.2
Units
V
V
V
mA
mA
µA
µA
µA
µA
µA
V
V
V
V
1. V
IL
min and V
IH
max are reference only and are not tested.
4
3350C–SEEPR–5/04
AT24C64B
AC Characteristics
Applicable over recommended operating range from T
AI
= -40°C to +85°C, V
CC
= +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
AT24C64B
1.8V – 3.6V
Symbol
f
SCL
t
LOW
t
HIGH
t
I
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
(1)
Notes:
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
(1)
Clock Low to Data Out Valid
Time the bus must be free before a new transmission can start
(2)
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time
(2)
Inputs Fall Time
(2)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
5.0V, 25°C, Page Mode
1M
0.6
200
5
1M
0.2
1.3
0.6
0.6
0
100
0.3
300
0.6
50
5
1.3
0.6
100
0.9
0.1
1.2
0.6
0.6
0
100
0.3
300
Parameter
Min
Max
400
1.2
0.6
50
0.9
Min
5.0V
Max
400
Units
kHz
µs
µs
ns
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
ms
Write
Cycles
1. This parameter is characterized and is not 100% tested (T
A
= 25°C)
2. This parameter is characterized and is not 100% tested.
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3350C–SEEPR–5/04
FPGA/CPLD
