AT25DN256
256-Kbit, 2.3V Minimum
SPI Serial Flash Memory with Dual-Read Support
PRELIMINARY DATASHEET
Features
Single 2.3V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual Output Read
104MHz Maximum Operating Frequency
Clock-to-Output (t
V
) of 6ns
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 256-Byte Page erase
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Full Chip Erase
Hardware Controlled Locking of Protected Sectors via WP Pin
128-byte, One-Time Programmable (OTP) Security Register
64 bytes factory programmed with a unique identifier
64 bytes user programmable
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
1.25ms Typical Page Program (256 Bytes) Time
35ms Typical 4-Kbyte Block Erase Time
250ms Typical 32-Kbyte Block Erase Time
Automatic Checking and Reporting of Erase/Program Failures
Software Controlled Reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
350nA Ultra Deep Power Down current (Typical)
7.5µA Deep Power-Down Current (Typical)
25uA Standby current (Typical)
6mA Active Read Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil)
8-pad Ultra Thin DFN (2 x 3 x 0.6mm)
8-lead TSSOP Package
DS-25DN256–039C–10/2014
1.
Description
The Adesto
®
AT25DN256 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer
based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The
flexible erase architecture of the AT25DN256, with its page erase granularity it is ideal for data storage as well, eliminating the
need for additional data storage devices.
The erase block sizes of the AT25DN256 have been optimized to meet the needs of today's code and data storage applications.
By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because certain code modules
and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that
occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space
efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device
density.
The device also contains a specialized OTP (One-Time Programmable) Security Register that can be used for purposes such as
unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc.
Specifically designed for use in many different systems, the AT25DN256 supports read, program, and erase operations with a
wide supply voltage range of 2.3V to 3.6V. No separate voltage is required for programming and erasing.
2.
Pin Descriptions and Pinouts
Pin Descriptions
Asserted
State
Table 2-1.
Symbol
Name and Function
CHIP SELECT:
Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in standby mode (not Deep Power-Down mode),
and the SO pin will be in a high-impedance state. When the device is deselected, data will not be
accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition
is required to end an operation. When ending an internally self-timed operation such as a program
or erase cycle, the device will not enter the standby mode until the completion of the operation.
SERIAL CLOCK:
This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is always
latched in on the rising edge of SCK, while output data on the SO pin is always clocked out on the
falling edge of SCK.
SERIAL INPUT:
The SI pin is used to shift data into the device. The SI pin is used for all data input
including command and address sequences. Data on the SI pin is always latched in on the rising
edge of SCK.
Type
CS
Low
Input
SCK
-
Input
SI (I/O
0
)
With the Dual-Output Read commands, the SI Pin becomes an output pin (I/O
0
) in conjunction with
other pins to allow two bits of data on (I/O
1-0
) to be clocked out on every falling edge of SCK.
To maintain consistency with the SPI nomenclature, the SI (I/O
0
) pin will be referenced as the SI
pin unless specifically addressing the Dual-I/O modes in which case it will be referenced as I/O
0.
Data present on the SI pin will be ignored whenever the device is deselected (CS is deasserted).
SERIAL OUTPUT:
The SO pin is used to shift data out from the device. Data on the SO pin is
always clocked out on the falling edge of SCK.
-
Input/
Output
SO
(I/O
1
)
With the Dual-Output Read commands, the SO Pin remains an output pin (I/O
1
) in conjunction with
other pins to allow two bits of data on (I/O
1-0
) to be clocked out on every falling edge of SCK.
To maintain consistency with the SPI nomenclature, the SO (I/O
1
) pin will be referenced as the SO
pin unless specifically addressing the Dual-I/O modes in which case it will be referenced as I/O
1.
The SO pin will be in a high-impedance state whenever the device is deselected (CS is
deasserted).
-
Input/
Output
AT25DN256
DS-25DN256–039C–10/2014
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Table 2-1.
Pin Descriptions (Continued)
Asserted
State
Symbol
Name and Function
WRITE PROTECT:
The WP pin controls the hardware locking feature of the device. Please refer
to
“Protection Commands and Features” on page 12
for more details on protection features and
the WP pin.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection will
not be used. However, it is recommended that the WP pin also be externally connected to V
CC
whenever possible.
HOLD:
The HOLD pin is used to temporarily pause serial communication without deselecting or
resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the
SI pin will be ignored, and the SO pin will be in a high-impedance state.
Type
WP
Low
Input
HOLD
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an
effect on internally self-timed operations such as a program or erase cycle. Please refer to
“Hold” on page 26
for additional details on the Hold operation.
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used.
However, it is recommended that the HOLD pin also be externally connected to V
CC
whenever
possible.
Low
Input
V
CC
GND
DEVICE POWER SUPPLY:
The V
CC
pin is used to supply the source voltage to the device.
Operations at invalid V
CC
voltages may produce spurious results and should not be attempted.
GROUND:
The ground reference for the power supply. GND should be connected to the system
ground.
-
Power
-
Power
Table 2-2.
Pinouts
Figure 2-3. 8-UDFN (Top View)
8
7
6
5
VCC
HOLD
SCK
SI
Figure 2-1. 8-SOIC Top View
CS
SO
WP
GND
1
2
3
4
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
Figure 2-2. 8-TSSOP Top View
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
AT25DN256
DS-25DN256–039C–10/2014
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3.
Block Diagram
Figure 3-1. Block Diagram
AT25DN256
DS-25DN256–039C–10/2014
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4.
Memory Array
To provide the greatest flexibility, the memory array of the AT25DN256 can be erased in three levels of granularity
including a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing
both code and data segments to reside in their own erase regions. The Memory Architecture Diagram illustrates the
breakdown of each erase level.
Figure 4-1. Memory Architecture Diagram
Block Erase Detail
32KB
Block Erase
(52h Command)
4KB
Block Erase
(20h Command)
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
Block Address
Range
007FFFh
006FFFh
005FFFh
004FFFh
003FFFh
002FFFh
001FFFh
000FFFh
–
–
–
–
–
–
–
–
007000h
006000h
005000h
004000h
003000h
002000h
001000h
000000h
Page Program Detail
1-256 Byte
Page Program
(02h Command)
256 Bytes
256 Bytes
256 Bytes
•••
Page Address
Range
007FFFh – 007F00h
007EFFh – 007E00h
007DFFh – 007D00h
32KB
256 Bytes
256 Bytes
256 Bytes
0002FFh – 000200h
0001FFh – 000100h
0000FFh – 000000h
5.
Device Operation
The AT25DN256 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the
SPI Master. The SPI Master communicates with the AT25DN256 via the SPI bus which is comprised of four signal lines:
Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the
SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25DN256
supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the
polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any
data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge
of SCK.
Figure 5-1. SPI Mode 0 and 3
CS
SCK
SI
MSB
LSB
SO
MSB
LSB
5.1
Dual Output Read
The ATx features a Dual-Output Read mode that allow two bits of data to be clocked out of the device every clock cycle
to improve throughput. To accomplish this, both the SI and SO pins are utilized as outputs for the transfer of data bytes.
With the Dual-Output Read Array command, the SI pin becomes an output along with the SO pin.
AT25DN256
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FPGA/CPLD
