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AT27RW1024-55JC

EEPROM, 64KX16, 55ns, Parallel, CMOS, PQCC44, PLASTIC, LCC-44

器件类别:存储    存储   

厂商名称:Atmel (Microchip)

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器件参数
参数名称
属性值
是否无铅
含铅
是否Rohs认证
不符合
厂商名称
Atmel (Microchip)
零件包装代码
LCC
包装说明
QCCJ, LDCC44,.7SQ
针数
44
Reach Compliance Code
compliant
ECCN代码
3A991.B.1.B.2
最长访问时间
55 ns
其他特性
17301504
命令用户界面
YES
数据轮询
NO
JESD-30 代码
S-PQCC-J44
JESD-609代码
e0
长度
16.5862 mm
内存密度
1048576 bit
内存集成电路类型
EEPROM
内存宽度
16
湿度敏感等级
2
功能数量
1
端子数量
44
字数
65536 words
字数代码
64000
工作模式
ASYNCHRONOUS
最高工作温度
70 °C
最低工作温度
组织
64KX16
封装主体材料
PLASTIC/EPOXY
封装代码
QCCJ
封装等效代码
LDCC44,.7SQ
封装形状
SQUARE
封装形式
CHIP CARRIER
并行/串行
PARALLEL
峰值回流温度(摄氏度)
225
电源
5 V
编程电压
12 V
认证状态
Not Qualified
座面最大高度
4.57 mm
最大待机电流
0.0001 A
最大压摆率
0.03 mA
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
J BEND
端子节距
1.27 mm
端子位置
QUAD
处于峰值回流温度下的最长时间
30
切换位
NO
宽度
16.5862 mm
文档预览
Features
Fast 5V Read Access Time - 35 ns
Command Table Architecture
– Internal Program Control and Timer
12V Program and Erase
– Fast Chip Erase Time - 0.5 Second Maximum
– Word-by-word Programming - 20 µs/Word Typical
Hardware Data Protection
Low-power CMOS Operation
– 100 µA Maximum Standby
– 30 mA Maximum Active at 5 MHz
JEDEC Standard Packages
– 44-lead PLCC
– 40-lead VSOP (10 mm x 14 mm)
Pin-compatible with Atmel’s AT27C1024 and AT49F1024/1025
High-reliability CMOS Technology
– 2000V ESD Protection
– 200 mA Latchup Immunity
CMOS and TTL Compatible Inputs and Outputs
100 Write Cycles Guaranteed
1-megabit
(64K x 16)
Rewriteable
PROM
AT27RW1024
Description
The AT27RW1024 is a low-power, high-performance 1,048,576-bit electrically-
rewriteable programmable read-only memory (RWPROM) organized 64K x 16 bits. It
requires only one 5V power supply in normal read mode operation. Any word can be
accessed in less than 35 ns, eliminating the need for speed reducing WAIT states.
(continued)
Pin Configurations
Pin Name
A0 - A15
CE
OE
WE
I/O0 - I/O15
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
A9
A10
A11
A12
A13
A14
A15
NC
WE
VCC
VPP
CE
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VSOP Type 1
10 x 14 mm
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
PLCC Top View
I/O13
I/O14
I/O15
CE
VPP
NC
VCC
WE
NC
A15
A14
I/O3
I/O2
I/O1
I/O0
OE
NC
A0
A1
A2
A3
A4
18
19
20
21
22
23
24
25
26
27
28
I/O12
I/O11
I/O10
I/O9
I/O8
GND
NC
I/O7
I/O6
I/O5
I/O4
7
8
9
10
11
12
13
14
15
16
17
6
5
4
3
2
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
Rev. 1415A–06/99
1
The x16 organization makes this part ideal for high-
performance 16- and 32-bit DSP and microprocessor
systems. The AT27RW1024 is pin-compatible with Atmel’s
AT49F1024/1025 and AT27C1024. In read mode, the
AT27RW1024 typically consumes 15 mA. Standby mode
supply current is typically less than 10 µA. Reprogramming
the AT27RW1024 is performed by erasing the entire chip
and then programming on a word-by-word basis. The
program and erase functions are performed with V
CC
= 5V
and V
PP
= 12V. Programming time is 20 µs per word typi-
cal. 100 program and erase cycles are guaranteed.
Block Diagram
VCC
GND
OE
WE
CE
DATA INPUTS/OUTPUTS
I/O15 - I/O0
16
OE, CE, AND WE
LOGIC
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y-GATING
MAIN MEMORY
(64K WORDS)
Y DECODER
ADDRESS
INPUTS
X DECODER
Device Operation
READ:
When CE and OE are low and WE is high, the data
stored at the memory location determined by the address
pins is asserted on the outputs. The outputs are put in the
high impedance state whenever CE or OE is high. This
dual-line control gives designers flexibility in preventing bus
contention.
CHIP ERASE:
The chip erase will erase all words to an
FFFFH. The chip erase command is a six bus cycle opera-
tion. The address (5555H) is latched on the falling edge of
the sixth cycle while the 10H data input is latched on the
rising edge of WE. The chip erase starts after the rising
edge of WE of the sixth cycle. Please see “Chip Erase
Cycle Waveforms” on page 7. The chip erase operation is
internally controlled; it will automatically time to completion.
After a chip erase, the device will return to the read mode.
Chip erase requires V
CC
= 5V and V
PP
= 12V.
WORD PROGRAMMING:
Once the memory array is
erased, the device is programmed (to a logical “0”) on a
word-by-word basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can
convert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified t
BP
cycle
time. Programming requires V
PP
= 12V and V
CC
= 5V.
PRODUCT IDENTIFICATION:
The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
HARDWARE DATA PROTECTION:
Hardware features
protect against inadvertent programs to the AT27RW1024
in the following ways: (a) V
CC
sense: if V
CC
is below 3.8V
(typical), the program function is inhibited. (b) Program
inhibit: holding any one of OE low, CE high or WE high
inhibits program cycles. (c) Noise filter: Pulses of less than
15 ns (typical) on the WE or CE inputs will not initiate a
program cycle.
2
AT27RW1024
AT27RW1024
Command Definition (in Hex)
Command
Sequence
Read
Chip Erase
Word Program
Product ID Entry
Product ID Exit
Note:
Bus
Cycles
1
6
4
3
1
1st Bus
Cycle
Addr
Addr
5555
5555
5555
xxxx
Data
D
OUT
AA
AA
AA
F0
2AAA
2AAA
2AAA
55
55
55
5555
5555
5555
80
A0
90
5555
Addr
AA
D
IN
2AAA
55
5555
10
2nd Bus
Cycle
Addr
Data
3rd Bus
Cycle
Addr
Data
4th Bus
Cycle
Addr
Data
5th Bus
Cycle
Addr
Data
6th Bus
Cycle
Addr
Data
The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
3
DC and AC Operating Range
AT27RW1024-35
Com.
Operating Temperature (Case)
Ind.
V
CC
Power Supply
-40°C - 85°C
5V
±
10%
-40°C - 85°C
5V
±
10%
-40°C - 85°C
5V
±
10%
-40°C - 85°C
5V
±
10%
0°C - 70°C
AT27RW1024-45
0°C - 70°C
AT27RW1024-55
0°C - 70°C
AT27RW1024-70
0°C - 70°C
Operating Modes
Mode
Read
Program/Erase
(2)
Standby
Program/Erase Inhibit
Program/Erase Verify
Output Disable
Product Identification
X
(4)
Hardware
V
IL
V
IL
V
IH
X
(4)
X
(4)
X
(4)
A1 - A15 = V
IL
, A9 = V
H
,
(3)
A0 = V
IL
A1 - A15 = V
IL
, A9 = V
H
,
(3)
A0 = V
IH
A0 = V
IL
, A1 - A15 = V
IL
A0 = V
IH
, A1 - A15 = V
IL
Manufacturer Code
(6)
Device Code
(6)
Manufacturer Code
(6)
Device Code
(6)
CE
V
IL
V
IL
V
IH
V
IL
X
(1)
X
(1)
X
(1)
OE
V
IL
V
IH
X
(1)
V
IH
X
(1)
V
IL
V
IH
WE
V
IH
V
IL
X
(1)
V
IL
V
IH
X
(1)
X
(1)
V
PP
X
(1)(7)
V
PP
X
(1)(7)
X
(1)(7)
V
PP
V
PP
X
(1)(7)
Ai
Ai
Ai
X
(1)
X
(1)
X
(1)
Ai
D
OUT
High Z
I/O
D
OUT
D
IN
/X
High Z
Software
(5)
Notes:
1.
2.
3.
4.
5.
6.
7.
X can be V
IL
or V
IH
.
Refer to AC Programming and Erasing Waveforms.
V
H
= 12.0V
±
0.5V.
X can be V
CC
or V
PP
.
See details under Software Product Identification Entry/Exit.
Manufacturer Code: 001EH, Device Code: 0051H.
For customers building field-upgradable systems, X can be 12.0V.
DC Characteristics
Symbol
I
LI
I
LO
I
SB1
I
SB2
I
CC
I
PP
V
IL
V
IH
V
OL
V
OH1
Parameter
Input Load Current
Output Leakage Current
V
CC
Standby Current CMOS
V
CC
Standby Current TTL
V
CC
Active Current
Program or Erase Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 2.1 mA
I
OH
= -400 µA
2.4
2.0
0.45
Condition
V
IN
= 0V to V
CC
V
I/O
= 0V to V
CC
CE = V
CC
- 0.3V to V
CC
CE = 2.0V to V
CC
f = 5 MHz; I
OUT
= 0 mA
Word Program, Chip Erase in Progress
Min
Max
10
10
100
1
30
25
0.8
Units
µA
µA
µA
mA
mA
mA
V
V
V
V
4
AT27RW1024
AT27RW1024
AC Read Characteristics
AT27RW1024-35
Symbol
t
ACC
t
CE(1)
t
OE(2)
t
DF(3)(4)
t
OH
Parameter
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
Output Hold from OE, CE or
Address, whichever occurred first
0
0
7
Min
Max
35
35
15
15
7
AT27RW1024-45
Min
Max
45
45
18
18
0
7
AT27RW1024-55
Min
Max
55
55
25
25
7
AT27RW1024-70
Min
Max
70
70
25
25
Units
ns
ns
ns
ns
ns
AC Read Waveforms
(1)(2)(3)(4)
Notes:
1. CE may be delayed up to t
ACC
- t
CE
after the address transition without impact on t
ACC
.
2. OE may be delayed up to t
CE
- t
OE
after the falling edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change
without impact on t
ACC
.
3. t
DF
is specified from OE or CE whichever occurs first (C
L
= 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
5.0V
1.8K
OUTPUT
PIN
1.3K
30 pF
t
R
, t
F
< 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C
(1)
Symbol
C
IN
C
OUT
Note:
Typ
4
8
Max
6
12
Units
pF
pF
Conditions
V
IN
= 0V
V
OUT
= 0V
1. This parameter is characterized and is not 100% tested.
5
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参数对比
与AT27RW1024-55JC相近的元器件有:AT27RW1024-45VI、AT27RW1024-55VC、AT27RW1024-45JI、AT27RW1024-55JI、AT27RW1024-70JI、AT27RW1024-45VC、AT27RW1024-35JI。描述及对比如下:
型号 AT27RW1024-55JC AT27RW1024-45VI AT27RW1024-55VC AT27RW1024-45JI AT27RW1024-55JI AT27RW1024-70JI AT27RW1024-45VC AT27RW1024-35JI
描述 EEPROM, 64KX16, 55ns, Parallel, CMOS, PQCC44, PLASTIC, LCC-44 EEPROM, 64KX16, 45ns, Parallel, CMOS, PDSO40, 10 X 14 MM, PLASTIC, VSOP-40 EEPROM, 64KX16, 55ns, Parallel, CMOS, PDSO40, 10 X 14 MM, PLASTIC, VSOP-40 EEPROM, 64KX16, 45ns, Parallel, CMOS, PQCC44, PLASTIC, LCC-44 EEPROM, 64KX16, 55ns, Parallel, CMOS, PQCC44, PLASTIC, LCC-44 EEPROM, 64KX16, 70ns, Parallel, CMOS, PQCC44, PLASTIC, LCC-44 EEPROM, 64KX16, 45ns, Parallel, CMOS, PDSO40, 10 X 14 MM, PLASTIC, VSOP-40 EEPROM, 64KX16, 35ns, Parallel, CMOS, PQCC44, PLASTIC, LCC-44
是否无铅 含铅 含铅 含铅 含铅 含铅 含铅 含铅 含铅
是否Rohs认证 不符合 不符合 不符合 不符合 不符合 不符合 不符合 不符合
厂商名称 Atmel (Microchip) Atmel (Microchip) Atmel (Microchip) Atmel (Microchip) Atmel (Microchip) Atmel (Microchip) Atmel (Microchip) Atmel (Microchip)
零件包装代码 LCC SOIC SOIC LCC LCC LCC SOIC LCC
包装说明 QCCJ, LDCC44,.7SQ TSOP1, TSSOP40,.56,20 TSOP1, TSSOP40,.56,20 QCCJ, LDCC44,.7SQ QCCJ, LDCC44,.7SQ QCCJ, LDCC44,.7SQ TSOP1, TSSOP40,.56,20 QCCJ, LDCC44,.7SQ
针数 44 40 40 44 44 44 40 44
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant compliant
ECCN代码 3A991.B.1.B.2 3A991.B.1.B.2 3A991.B.1.B.2 3A991.B.1.B.2 3A991.B.1.B.2 3A991.B.1.B.2 3A991.B.1.B.2 3A991.B.1.B.2
最长访问时间 55 ns 45 ns 55 ns 45 ns 55 ns 70 ns 45 ns 35 ns
其他特性 17301504 17301504 17301504 17301504 17301504 17301504 17301504 17301504
命令用户界面 YES YES YES YES YES YES YES YES
数据轮询 NO NO NO NO NO NO NO NO
JESD-30 代码 S-PQCC-J44 R-PDSO-G40 R-PDSO-G40 S-PQCC-J44 S-PQCC-J44 S-PQCC-J44 R-PDSO-G40 S-PQCC-J44
JESD-609代码 e0 e0 e0 e0 e0 e0 e0 e0
长度 16.5862 mm 12.4 mm 12.4 mm 16.5862 mm 16.5862 mm 16.5862 mm 12.4 mm 16.5862 mm
内存密度 1048576 bit 1048576 bit 1048576 bit 1048576 bit 1048576 bit 1048576 bit 1048576 bit 1048576 bit
内存集成电路类型 EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM
内存宽度 16 16 16 16 16 16 16 16
功能数量 1 1 1 1 1 1 1 1
端子数量 44 40 40 44 44 44 40 44
字数 65536 words 65536 words 65536 words 65536 words 65536 words 65536 words 65536 words 65536 words
字数代码 64000 64000 64000 64000 64000 64000 64000 64000
工作模式 ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS
最高工作温度 70 °C 85 °C 70 °C 85 °C 85 °C 85 °C 70 °C 85 °C
最低工作温度 - -40 °C - -40 °C -40 °C -40 °C - -40 °C
组织 64KX16 64KX16 64KX16 64KX16 64KX16 64KX16 64KX16 64KX16
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 QCCJ TSOP1 TSOP1 QCCJ QCCJ QCCJ TSOP1 QCCJ
封装等效代码 LDCC44,.7SQ TSSOP40,.56,20 TSSOP40,.56,20 LDCC44,.7SQ LDCC44,.7SQ LDCC44,.7SQ TSSOP40,.56,20 LDCC44,.7SQ
封装形状 SQUARE RECTANGULAR RECTANGULAR SQUARE SQUARE SQUARE RECTANGULAR SQUARE
封装形式 CHIP CARRIER SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE CHIP CARRIER CHIP CARRIER CHIP CARRIER SMALL OUTLINE, THIN PROFILE CHIP CARRIER
并行/串行 PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
峰值回流温度(摄氏度) 225 NOT SPECIFIED NOT SPECIFIED 225 225 225 NOT SPECIFIED 225
电源 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
编程电压 12 V 12 V 12 V 12 V 12 V 12 V 12 V 12 V
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 4.57 mm 1.2 mm 1.2 mm 4.57 mm 4.57 mm 4.57 mm 1.2 mm 4.57 mm
最大待机电流 0.0001 A 0.0001 A 0.0001 A 0.0001 A 0.0001 A 0.0001 A 0.0001 A 0.0001 A
最大压摆率 0.03 mA 0.03 mA 0.03 mA 0.03 mA 0.03 mA 0.03 mA 0.03 mA 0.03 mA
最大供电电压 (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
最小供电电压 (Vsup) 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V
标称供电电压 (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
表面贴装 YES YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 COMMERCIAL INDUSTRIAL COMMERCIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL COMMERCIAL INDUSTRIAL
端子面层 Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
端子形式 J BEND GULL WING GULL WING J BEND J BEND J BEND GULL WING J BEND
端子节距 1.27 mm 0.5 mm 0.5 mm 1.27 mm 1.27 mm 1.27 mm 0.5 mm 1.27 mm
端子位置 QUAD DUAL DUAL QUAD QUAD QUAD DUAL QUAD
处于峰值回流温度下的最长时间 30 NOT SPECIFIED NOT SPECIFIED 30 30 30 NOT SPECIFIED 30
切换位 NO NO NO NO NO NO NO NO
宽度 16.5862 mm 10 mm 10 mm 16.5862 mm 16.5862 mm 16.5862 mm 10 mm 16.5862 mm
湿度敏感等级 2 - - 2 2 2 - 2
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