Features
•
High Performance, Low Power AVR
®
32 UC 32-Bit Microcontroller
– Compact Single-cycle RISC Instruction Set Including DSP Instruction Set
– Read-Modify-Write Instructions and Atomic Bit Manipulation
– Performing up to 1.39 DMIPS / MHz
Up to 83 DMIPS Running at 60 MHz from Flash
Up to 46 DMIPS Running at 30 MHz from Flash
– Memory Protection Unit
Multi-hierarchy Bus System
– High-Performance Data Transfers on Separate Buses for Increased Performance
– 7 Peripheral DMA Channels Improves Speed for Peripheral Communication
Internal High-Speed Flash
– 512K Bytes, 256K Bytes, 128K Bytes, 64K Bytes Versions
– Single Cycle Access up to 30 MHz
– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
– 4ms Page Programming Time and 8ms Full-Chip Erase Time
– 100,000 Write Cycles, 15-year Data Retention Capability
– Flash Security Locks and User Defined Configuration Area
Internal High-Speed SRAM, Single-Cycle Access at Full Speed
– 96K Bytes (512KB Flash), 32K Bytes (256KB and 128KB Flash), 16K Bytes (64KB
Flash)
Interrupt Controller
– Autovectored Low Latency Interrupt Service with Programmable Priority
System Functions
– Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator
– Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL) allowing
Independant CPU Frequency from USB Frequency
– Watchdog Timer, Real-Time Clock Timer
Universal Serial Bus (USB)
– Device 2.0 and Embedded Host Low Speed and Full Speed
– Flexible End-Point Configuration and Management with Dedicated DMA Channels
– On-chip Transceivers Including Pull-Ups
– USB Wake Up from Sleep Functionality
One Three-Channel 16-bit Timer/Counter (TC)
– Three External Clock Inputs, PWM, Capture and Various Counting Capabilities
One 7-Channel 20-bit Pulse Width Modulation Controller (PWM)
Three Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
– Independant Baudrate Generator, Support for SPI, IrDA and ISO7816 interfaces
– Support for Hardware Handshaking, RS485 Interfaces and Modem Line
One Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals
One Synchronous Serial Protocol Controller
– Supports I
2
S and Generic Frame-Based Protocols
One Master/Slave Two-Wire Interface (TWI), 400kbit/s I
2
C-compatible
One 8-channel 10-bit Analog-To-Digital Converter, 384ks/s
16-bit Stereo Audio Bitstream DAC
– Sample Rate Up to 50 KHz
QTouch
®
Library Support
– Capacitive Touch Buttons, Sliders, and Wheels
– QTouch
®
and QMatrix
®
Acquisition
•
•
•
•
•
32-bit AVR
®
Microcontroller
AT32UC3B0512
AT32UC3B0256
AT32UC3B0128
AT32UC3B064
AT32UC3B1512
AT32UC3B1256
AT32UC3B1128
AT32UC3B164
Preliminary
Summary
•
•
•
•
•
•
•
•
•
•
32059IS–06/2010
•
On-Chip Debug System (JTAG interface)
– Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace
•
64-pin TQFP/QFN (44 GPIO pins), 48-pin TQFP/QFN (28 GPIO pins)
•
5V Input Tolerant I/Os, including 4 high-drive pins
•
Single 3.3V Power Supply or Dual 1.8V-3.3V Power Supply
1. Description
The AT32UC3B is a complete System-On-Chip microcontroller based on the AVR32 UC RISC
processor running at frequencies up to 60 MHz. AVR32 UC is a high-performance 32-bit RISC
microprocessor core, designed for cost-sensitive embedded applications, with particular empha-
sis on low power consumption, high code density and high performance.
The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt con-
troller for supporting modern operating systems and real-time operating systems.
Higher computation capability is achieved using a rich set of DSP instructions.
The AT32UC3B incorporates on-chip Flash and SRAM memories for secure and fast access.
The Peripheral Direct Memory Access controller enables data transfers between peripherals and
memories without processor involvement. PDCA drastically reduces processing overhead when
transferring continuous and large data streams between modules within the MCU.
The Power Manager improves design flexibility and security: the on-chip Brown-Out Detector
monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external
oscillator sources, a Real-Time Clock and its associated timer keeps track of the time.
The Timer/Counter includes three identical 16-bit timer/counter channels. Each channel can be
independently programmed to perform frequency measurement, event counting, interval mea-
surement, pulse generation, delay timing and pulse width modulation.
The PWM modules provides seven independent channels with many configuration options
including polarity, edge alignment and waveform non overlap control. One PWM channel can
trigger ADC conversions for more accurate close loop control implementations.
The AT32UC3B also features many communication interfaces for communication intensive
applications. In addition to standard serial interfaces like UART, SPI or TWI, other interfaces like
flexible Synchronous Serial Controller and USB are available.
The Synchronous Serial Controller provides easy access to serial communication protocols and
audio standards like I
2
S, UART or SPI.
The Full-Speed USB 2.0 Device interface supports several USB Classes at the same time
thanks to the rich End-Point configuration. The Embedded Host interface allows device like a
USB Flash disk or a USB printer to be directly connected to the processor.
Atmel offers the QTouch library for embedding capacitive touch buttons, sliders, and wheels
functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers
robust sensing and included fully debounced reporting of touch keys and includes Adjacent Key
Suppression
®
(AKS
®
) technology for unambiguous detection of key events. The easy-to-use
QTouch Suite toolchain allows you to explore, develop, and debug your own touch applications.
AT32UC3B integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive
real-time trace, full-speed read/write memory access in addition to basic runtime control. The
Nanotrace interface enables trace feature for JTAG-based debuggers.
2. Overview
2.1
Blockdiagram
Block diagram
TCK
MEMORY INTERFACE
TDO
TDI
TMS
Figure 2-1.
JTAG
INTERFACE
MCKO
MDO[5..0]
MSEO[1..0]
EVTI_N
EVTO_N
LOCAL BUS
INTERFACE
FAST GPIO
NEXUS
CLASS 2+
OCD
UC CPU
MEMORY PROTECTION UNIT
INSTR
INTERFACE
DATA
INTERFACE
16/32/96 KB
SRAM
USB
INTERFACE
DMA
S
M
S
FLASH
CONTROLLER
VBUS
D+
D-
ID
VBOF
M
M
HIGH SPEED
BUS MATRIX
M
S
64/128/
256/512 KB
FLASH
S
M
S
CONFIGURATION
REGISTERS BUS
HSB
PB
HSB
HSB-PB
BRIDGE B
GENERAL PURPOSE IOs
HSB-PB
BRIDGE A
PB
PERIPHERAL
DMA
CONTROLLER
PA
PB
EXTINT[7..0]
KPS[7..0]
NMI
EXTERNAL
INTERRUPT
CONTROLLER
REAL TIME
COUNTER
PDC
USART1
RXD
TXD
CLK
RTS, CTS
DSR, DTR, DCD, RI
RXD
TXD
CLK
RTS, CTS
SCK
MISO, MOSI
NPCS[3..0]
GENERAL PURPOSE IOs
INTERRUPT
CONTROLLER
PA
PB
USART0
USART2
PDC
WATCHDOG
TIMER
115 kHz
RCOSC
XIN32
XOUT32
XIN0
XOUT0
XIN1
XOUT1
SERIAL
PERIPHERAL
INTERFACE
SYNCHRONOUS
SERIAL
CONTROLLER
PDC
TX_CLOCK, TX_FRAME_SYNC
TX_DATA
RX_CLOCK, RX_FRAME_SYNC
RX_DATA
POWER
MANAGER
CLOCK
GENERATOR
CLOCK
CONTROLLER
SLEEP
CONTROLLER
RESET
CONTROLLER
32 KHz
OSC
OSC0
OSC1
PLL0
PLL1
GCLK[3..0]
RESET_N
A[2..0]
B[2..0]
CLK[2..0]
PDC
TWO-WIRE
INTERFACE
ANALOG TO
DIGITAL
CONVERTER
AUDIO
BITSTREAM
DAC
PULSE WIDTH
MODULATION
CONTROLLER
PDC
SCL
SDA
PDC
AD[7..0]
ADVREF
PDC
DATA[1..0]
DATAN[1..0]
TIMER/COUNTER
PWM[6..0]
3. Configuration Summary
The table below lists all AT32UC3B memory and package configurations:
Table 3-1.
Device
AT32UC3B0512
AT32UC3B0256
AT32UC3B0128
AT32UC3B064
AT32UC3B1512
AT32UC3B1256
AT32UC3B1128
AT32UC3B164
Flash
512 Kbytes
256 Kbytes
128 Kbytes
64 Kbytes
512 Kbytes
256 Kbytes
128 Kbytes
64 Kbytes
Memory and Package Configurations
SSC
1
1
1
1
0
0
0
0
ADC
8
8
8
8
6
6
6
6
ABDAC
1
0
0
0
1
0
0
0
OSC
2
2
2
2
1
1
1
1
USB Configuration
Mini-Host + Device
Mini-Host + Device
Mini-Host + Device
Mini-Host + Device
Device
Device
Device
Device
Package
64 lead TQFP/QFN
64 lead TQFP/QFN
64 lead TQFP/QFN
64 lead TQFP/QFN
48 lead QFN
48 lead TQFP/QFN
48 lead TQFP/QFN
48 lead TQFP/QFN
SRAM
96 Kbytes
32 Kbytes
32 Kbytes
16 Kbytes
96 Kbytes
32 Kbytes
16 Kbytes
16 Kbytes
