Features
•
Compatible with MCS
®
-51 Products
•
12K Bytes of In-System Programmable (ISP) Flash Program Memory
– SPI Serial Interface for Program Downloading
– Endurance: 10,000 Write/Erase Cycles
2K Bytes EEPROM Data Memory
– Endurance: 100,000 Write/Erase Cycles
64-byte User Signature Array
2.7V to 5.5V Operating Range
Fully Static Operation: 0 Hz to 24 MHz (in x1 and x2 Modes)
Three-level Program Memory Lock
256 x 8-bit Internal RAM
32 Programmable I/O Lines
Three 16-bit Timer/Counters
Nine Interrupt Sources
Enhanced UART Serial Port with Framing Error Detection and Automatic
Address Recognition
Enhanced SPI (Double Write/Read Buffered) Serial Interface
Low-power Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
Programmable Watchdog Timer
Dual Data Pointer
Power-off Flag
Flexible ISP Programming (Byte and Page Modes)
– Page Mode: 64 Bytes/Page for Code Memory, 32 Bytes/Page for Data Memory
Four-level Enhanced Interrupt Controller
Programmable and Fuseable x2 Clock Option
Internal Power-on Reset
42-pin PDIP Package Option for Reduced EMC Emission
Green (Pb/Halide-free) Packaging Option
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8-bit
Microcontroller
with 12K Bytes
Flash and 2K
Bytes EEPROM
AT89S8253
1. Description
The AT89S8253 is a low-power, high-performance CMOS 8-bit microcontroller with
12K bytes of In-System Programmable (ISP) Flash program memory and 2K bytes of
EEPROM data memory. The device is manufactured using Atmel’s high-density non-
volatile memory technology and is compatible with the industry-standard MCS-51
instruction set and pinout. The on-chip downloadable Flash allows the program mem-
ory to be reprogrammed in-system through an SPI serial interface or by a
conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU
with downloadable Flash on a monolithic chip, the Atmel AT89S8253 is a powerful
microcontroller which provides a highly-flexible and cost-effective solution to many
embedded control applications.
3286L–MICRO–8/08
The AT89S8253 provides the following standard features: 12K bytes of In-System Programma-
ble Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32 I/O lines, programmable watchdog timer,
two data pointers, three 16-bit timer/counters, a six-vector, four-level interrupt architecture, a full
duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S8253 is designed
with static logic for operation down to zero frequency and supports two software selectable
power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,
serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM
contents but freezes the oscillator, disabling all other chip functions until the next external inter-
rupt or hardware reset.
The on-board Flash/EEPROM is accessible through the SPI serial interface. Holding RESET
active forces the SPI bus into a serial programming interface and allows the program memory to
be written to or read from, unless one or more lock bits have been activated.
2. Pin Configurations
2.1
40P6 – 40-lead PDIP
(T2) P1.0
(T2 EX) P1.1
P1.2
P1.3
(SS) P1.4
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)
2.2
44A – 44-lead TQFP
P1.4 (SS)
P1.3
P1.2
P1.1 (T2 EX)
P1.0 (T2)
NC
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
1
2
3
4
5
6
7
8
9
10
11
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
2
AT89S8253
3286L–MICRO–8/08
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
GND
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
12
13
14
15
16
17
18
19
20
21
22
AT89S8253
2.3
44J – 44-lead PLCC
P1.4 (SS)
P1.3
P1.2
P1.1 (T2 EX)
P1.0 (T2)
NC
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
2.4
42PS6 – PDIP
RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
PWRGND
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
(A13) P2.5
(A14) P2.6
(A15) P2.7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P1.7 (SCK)
P1.6 (MISO)
P1.5 (MOSI)
P1.4 (SS)
P1.3
P1.2
P1.1 (T2EX)
P1.0 (T2)
VDD
PWRVDD
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
ALE/PROG
PSEN
3. Pin Description
3.1
VCC
Supply voltage (all packages except 42-PDIP).
3.2
GND
Ground (all packages except 42-PDIP; for 42-PDIP GND connects only the logic core and the
embedded program/data memories).
3.3
VDD
Supply voltage for the 42-PDIP which connects only the logic core and the embedded pro-
gram/data memories.
3.4
PWRVDD
Supply voltage for the 42-PDIP which connects only the I/O Pad Drivers.
The application board
must
connect both VDD and PWRVDD to the board supply voltage.
3
3286L–MICRO–8/08
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
NC
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
18
19
20
21
22
23
24
25
26
27
28
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
6
5
4
3
2
1
44
43
42
41
40
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
3.5
PWRGND
Ground for the 42-PDIP which connects only the I/O Pad Drivers. PWRGND and GND are
weakly connected through the common silicon substrate, but not through any metal links. The
application board
must
connect both GND and PWRGND to the board ground.
3.6
Port 0
Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink six TTL
inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses
to external program and data memory. In this mode, P0 has internal pull-ups.
Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-
ing program verification.
External pull-ups are required during program verification.
3.7
Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can
sink/source six TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the weak
internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being
pulled low will source current (I
IL
,150
µ
A typical) because of the weak internal pull-ups.
Some Port 1 pins provide additional functions. P1.0 and P1.1 can be configured to be the
timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX),
respectively.
Furthermore, P1.4, P1.5, P1.6, and P1.7 can be configured as the SPI slave port select, data
input/output and shift clock input/output pins as shown in the following table.
Port Pin
P1.0
P1.1
P1.4
P1.5
P1.6
P1.7
Alternate Functions
T2 (external count input to Timer/Counter 2), clock-out
T2EX (Timer/Counter 2 capture/reload trigger and direction control)
SS (Slave port select input)
MOSI (Master data output, slave data input pin for SPI channel)
MISO (Master data input, slave data output pin for SPI channel)
SCK (Master clock output, slave clock input pin for SPI channel)
Port 1 also receives the low-order address bytes during Flash programming and verification.
3.8
Port 2
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can
sink/source six TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the weak
internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being
pulled low will source current (I
IL
,150
µ
A typical) because of the weak internal pull-ups.
Port 2 emits the high-order address byte during fetches from external program memory and dur-
ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this
application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2
Special Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash
programming and verification.
4
AT89S8253
3286L–MICRO–8/08
AT89S8253
3.9
Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can
sink/source six TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the weak
internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being
pulled low will source current (I
IL
,150
µ
A typical) because of the weak internal pull-ups.
Port 3 receives some control signals for Flash programming and verification.
Port 3 also serves the functions of various special features of the AT89S8253, as shown in the
following table.
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Note:
Alternate Functions
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
(1)
INT1 (external interrupt 1)
(1)
T0 (timer 0 external input)
T1 (timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
1. All pins in ports 1 and 2 and almost all pins in port 3 (the exceptions are P3.2 INT0 and P3.3
INT1) have their inputs disabled in the Power-down mode. Port pins P3.2 (INT0) and P3.3
(INT1) are active even in Power-down mode (to be able to sense an interrupt request to exit
the Power-down mode) and as such still have their weak internal pull-ups turned on.
3.10
RST
Reset input. A high on this pin for at least two machine cycles while the oscillator is running
resets the device.
3.11
ALE/PROG
Address Latch Enable. ALE/PROG is an output pulse for latching the low byte of the address (on
its falling edge) during accesses to external memory. This pin is also the program pulse input
(PROG) during Flash programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be
used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur-
ing each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of the AUXR SFR at location 8EH. With
the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly
pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execu-
tion mode.
3.12
PSEN
Program Store Enable. PSEN is the read strobe to external program memory (active low).
When the AT89S8253 is executing code from external program memory, PSEN is activated
twice each machine cycle, except that two PSEN activations are skipped during each access to
external data memory.
5
3286L–MICRO–8/08
