SAM9N12/SAM9CN11/SAM9CN12
Atmel | SMART ARM-based Embedded MPU
DATASHEET
Description
The Atmel
®
| SMART SAM9N and SAM9CN ARM926EJ-S™-based embedded
MPUs offer the frequently-requested combination of user interface functionality
and high data rate connectivity, with LCD controller, resistive touchscreen,
multiple UARTs, SPI, I2C, full-speed USB Host and Device and SDIO.
These eMPUs support the latest generation of LPDDR/DDR2 and NAND Flash
memory interfaces for program and data storage. An internal 133 MHz multi-layer
bus architecture associated with eight DMA channels and distributed memory—
including a 32-Kbyte SRAM—sustains the high bandwidth required by the
processor and the high-speed peripherals.
The SAM9CN devices offer on-chip hardware accelerators with DMA support that
enable high-speed data encryption and authentication of transferred data or
applications. Supported standards are up to 256-bit AES, and FIPS Publication
180-2 compliant SHA1 and SHA256. A True Random Number Generator is
embedded for key generation and exchange protocols. The devices also feature
fuse bits for crypto key (SAM9CN12), user configuration (SAM9N12 and
SAM9CN11) and device configuration (all). The SAM9CN12 includes a secure
Boot ROM; the SAM9N12 and SAM9CN11 include a standard Boot ROM.
The I/Os support 1.8V or 3.3V operation and are independently configurable for
the memory interface and peripheral I/Os. This feature eliminates the need for any
external level shifters, while 0.8mm ball pitch packages lower PCB cost and
complexity.
The SAM9N and SAM9CN power management controllers feature efficient clock
gating and a battery backup section that minimizes power consumption in active
and standby modes. The following table presents the embedded features of each
device.
Device Configuration
Feature
Standard Boot with BSC
Secure Boot
TRNG
AES
SHA
SAM9N12
–
–
–
SAM9CN11
–
SAM9CN12
–
Atmel-11063L-ATARM-SAM9N12-SAM9CN11-SAM9CN12-Datasheet_28-Oct-15
Features
Core
̶
ARM926EJ-S ARM
®
Thumb
®
Processor running up to 400 MHz
̶
16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit
Memories
̶
One 128-Kbyte internal ROM embedding standard or secure bootstrap routine
̶
One 32-Kbyte internal SRAM, single-cycle access at system speed
̶
32-bit External Bus Interface supporting 8-bank DDR2/LPDDR, SDR/LPSDR, Static Memories
̶
MLC/SLC NAND Controller, with up to 24-bit Programmable Multibit Error Correction Code (PMECC)
System running up to 133 MHz
̶
Power-on Reset, Reset Controller, Shutdown Controller, Periodic Interval Timer, Watchdog Timer and Real Time
Clock
̶
Boot Mode Select Option, Remap Command
̶
Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators
̶
Selectable 32768 Hz Low-power Oscillator, 16 MHz Oscillator, one PLL for the system and one PLL optimized
for USB
̶
Six 32-bit-layer AHB Bus Matrix
̶
Dual Peripheral Bridge with dedicated programmable clock
̶
One dual port 8-channel DMA Controller
̶
Advanced Interrupt Controller (AIC)
̶
Two Programmable External Clock Signals
Low-power Mode
̶
Shutdown Controller with four 32-bit General-purpose Backup Registers
̶
Clock Generator and Power Management Controller
̶
Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
Peripherals
̶
LCD Controller
̶
USB Device Full Speed with dedicated On-chip Transceiver
̶
USB Host Full Speed with dedicated On-chip Transceiver
̶
One High speed SD card and SDIO Host Controller
̶
Two Master/Slave Serial Peripheral Interfaces (SPI)
̶
Two 3-channel 32-bit Timer/Counters (TC)
̶
One Synchronous Serial Controller (SSC)
̶
One 4-channel 16-bit PWM Controller
̶
Two 2-wire Interfaces (TWI)
̶
Four Universal Synchronous Asynchronous Receiver Transmitters (USART)
̶
Two Universal Asynchronous Receiver Transmitters (UART)
̶
One Debug Unit (DBGU)
̶
One 12-channel 10-bit Analog-to-Digital Converter with up to 5-wire resistive Touchscreen support
Safety
̶
Crystal Failure Detection
̶
Independent Watchdog
̶
Power-on Reset Cells
̶
Register Write Protection
̶
SHA (SHA1 and SHA256) Compliant with FIPS Publication 180-2 (SAM9CN11/SAM9CN12 devices)
2
SAM9N12-SAM9CN11-SAM9CN12 [DATASHEET]
Atmel-11063L-ATARM-SAM9N12-SAM9CN11-SAM9CN12-Datasheet_28-Oct-15
Cryptography
̶
True Random Number Generator (TRNG) compliant with NIST Special Publication 800-22
̶
AES 256-, 192-, 128-bit Key Algorithm compliant with FIPS Publication 197 (SAM9CN11/SAM9CN12 devices)
̶
256 Fuse bits for crypto key and 64 Fuse bits for device configuration, including JTAG disable and forced boot
from the on-chip ROM
I/O
̶
̶
̶
̶
Four 32-bit Parallel Input/Output Controllers
105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os
Input Change Interrupt Capability on Each I/O Line, optional Schmitt Trigger input
Individually Programmable Open-drain, Pull-up and Pull-down Resistor, Synchronous Output
Packages
̶
217-ball BGA, pitch 0.8 mm
̶
247-ball BGA, pitch 0.5 mm
SAM9N12-SAM9CN11-SAM9CN12 [DATASHEET]
Atmel-11063L-ATARM-SAM9N12-SAM9CN11-SAM9CN12-Datasheet_28-Oct-15
3
1.
Block Diagram
SAM9N12/CN11/CN12 Block Diagram
NC
23 SY
AT DH
M
W
DD LC
DP
LC C,
C
–
T0 YN
K
, L
SP
DADVS
DPC
DEN
DDI
D
LC LC
LC
LD
LC
4
Atmel-11063L-ATARM-SAM9N12-SAM9CN11-SAM9CN12-Datasheet_28-Oct-15
Figure 1-1.
POR
RSTC
POR
VDDCORE
* Except SAM9N12
DMA
DMA
PIOA
PIOB
PIOD
PIOC
AES *
SHA *
Peripheral
Bridge
SRAM
32 Kbytes
Peripheral
Bridge
TRNG
NAND Flash
Controller
PMECC
PMERRLOC
APB
DMA
DMA
SSC
FIFO
DMA
HSMCI0
SD/SDIO
DMA
TWI0
TWI1
PWM
DMA
USART0
USART1
USART2
USART3
DMA
UART0
UART1
SPI0
SPI1
TC0
TC1
TC2
TC3
TC4
TC5
DMA
12-channel
10-bit ADC
Touchscreen
DPRAM
USB FS
Device
Transceiver
PIO
CT
RT
S0–
SC
S0–
3
RDK0
3
–3
TX
X0–
UR
D0
3
D
–3
UT X0
XD –U
0– RD
UT X1
TC
XD
LK
TI 0
O –T
1
TI A0 C
O –T LK
B0 IO 5
–T A
5
TS
IOB
AD
5
AD T
AD 0/ RG
X
AD 1/X P/
3/ AD M/ UL
YM 2/ U
/SYP/ R
G
PA
E LL
D5 AD NS
–G 4/L E
P R
AD AD
1
VD VR 1
DA EF
G N
ND A
AN
A
T
TW W
D
CK 0–
0– TW
TW D
CK1
PW
1
M
0–
PW
M
3
0_
C
CI
DA
0_
CK
NP
NPCS
C 3
NP S2
NPCS
C 1
SP S0
M CK
O
M SI
IS
O
TK
TF
TD
RD
RF
RK
CI
M
I0
C
A
_D
M
0–
M
M
C
I
D
0_
DD
M
DD
P
A3
PIO
SAM9N12-SAM9CN11-SAM9CN12 [DATASHEET]
CK
RT
SE
G
TA
J
RS
T
L
TD
TDI
TMO
TC S
K
NT
System Controller
PCK0–PCK1
FIQ
IRQ
DRXD
DTXD
PIO
JTAG / Boundary Scan
Transceiver
In-Circuit Emulator
BM
HD
P
HD
M
S
PIO
Fuse Box
EBI
USB FS
OHCI
AIC
DBGU
PLLA
PLLB
PMC
ARM926EJ-S
ICache
16 Kbytes
MMU
DCache
16 Kbytes
LCD
8-ch
DMA
Bus Interface
DMA
DMA
DDR2/LPDDR
SDR/LPSDR
Controller
I
ROM
128 Kbytes
D
Static
Memory
Controller
XIN
XOUT
16 MHz
XTAL Osc.
12 MHz
RC Osc.
PIT
WDT
128-bit
GPBR
RC Osc.
RTC
Backup Section
XIN32
XOUT32
SHDN
WKUP
VDDBU
NRST
32 kHz
XTAL Osc
SHDWC
D0–D15
A0/NBS0
A1/NBS2/NWR2/DQM2
A2–A15, A19
A16/BA0
A17/BA1
A18/BA2
NCS0
NCS1/SDCS
NRD
NWR0/NWE
NWR1/NBS1
NWR3/NBS3/DQM3
SDCK, #SDCK, SDCKE
RAS, CAS
SDWE, SDA10
DQM[0..1]
DQS[0..1]
Multi-Layer AHB Matrix
NWAIT
A20–A25
D16–D31
NCS2, NCS3, NCS4, NCS5
NANDOE, NANDWE
NANDALE, NANDCLE
NANDCS
2.
Signal Description
Table 2-1
gives details on the signal names classified by peripheral.
Table 2-1.
Signal Name
Signal Description List
Function
Clocks, Oscillators and PLLs
XIN
XOUT
XIN32
XOUT32
PCK0–PCK1
Main Oscillator Input
Main Oscillator Output
Slow Clock Oscillator Input
Slow Clock Oscillator Output
Programmable Clock Output
Shutdown, Wakeup Logic
SHDN
WKUP
Shut-Down Control
Wake-Up Input
ICE and JTAG
TCK
TDI
TDO
TMS
JTAGSEL
RTCK
Test Clock
Test Data In
Test Data Out
Test Mode Select
JTAG Selection
Return Test Clock
Reset/Test
NRST
NTRST
BMS
Microcontroller Reset
Test Reset Signal
Boot Mode Select
Debug Unit - DBGU
DRXD
DTXD
Debug Receive Data
Debug Transmit Data
Advanced Interrupt Controller - AIC
IRQ
FIQ
External Interrupt Input
Fast Interrupt Input
PIO Controller - PIOA / PIOB / PIOC / PIOD
PA0–PA31
PB0–PB18
PC0–PC31
PD0–PD21
Parallel IO Controller A
Parallel IO Controller B
Parallel IO Controller C
Parallel IO Controller D
I/O
I/O
I/O
I/O
Input
Input
Input
Output
I/O
Input
Input
Low
Input
Input
Output
Input
Input
Output
Output
Input
Input
Output
Input
Output
Output
Type
Active Level
SAM9N12-SAM9CN11-SAM9CN12 [DATASHEET]
Atmel-11063L-ATARM-SAM9N12-SAM9CN11-SAM9CN12-Datasheet_28-Oct-15
5
