Features
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Contactless Read/Write Data Transmission
Radio Frequency f
RF
from 100 kHz to 150 kHz
e5550, e5551, T5557 Binary Compatible
Extended Mode
Small Size, Configurable for ISO/IEC 11784/785 Compatibility
75 pF On-chip Resonant Capacitor (Mask Option)
7
×
32-bit EEPROM Data Memory Including 32-bit Password
Separate 64-bit Memory for Traceability Data
32-bit Configuration Register in EEPROM to Setup:
– Data Rate
• RF/2 to RF/128, Binary Selectable, or
• Fixed e5550 Data Rates
– Modulation/Coding
• FSK, PSK, Manchester, Bi-phase, NRZ
– Other Options
• Password Mode
• Max Block Feature
• Answer-On-Request (AOR) Mode
• Inverse Data Output
• Direct Access Mode
• Sequence Terminator(s)
• Write Protection (Through Lock-bit per Block)
• Fast Write Method (5 Kbps versus 2 Kbps)
• OTP Functionality
• POR Delay up to 67 ms
Multifunctional
330-bit
Read/Write RF
Identification IC
ATA5567
1. Description
The ATA5567 is a contactless R/W IDentification IC (IDIC
®
) for applications in the
125-kHz frequency range. A single coil, connected to the chip, serves as the IC’s
power supply and bi-directional communication interface. The antenna and chip
together form a transponder or tag.
The on-chip 330-bit EEPROM (10 blocks, 33 bits each) can be read and written block-
wise from a reader. Block 0 is reserved for setting the operation modes of the
ATA5567 tag. Block 7 may contain a password to prevent unauthorized writing.
Data is transmitted from the IDIC using load modulation. This is achieved by damping
the RF field with a resistive load between the two terminals Coil 1 and Coil 2. The IC
receives and decodes 100% amplitude-modulated (OOK) pulse-interval-encoded bit
streams from the base station or reader.
4874F–RFID–07/08
2. System Block Diagram
Figure 2-1.
RFID System Using ATA5567 Tag
Transponder
Power
Reader
or
Base station
Coil interface
Controller
Memory
Data
1
)
ATA5567
1)
Mask option
3. ATA5567 – Building Blocks
Figure 3-1.
Block Diagram
POR
Modulation
Coil 1
Analog front end
Write
decoder
Mode register
Memory
(330-bit
EEPROM)
Controller
Bit-rate
generator
Input register
1
)
Coil 2
Test logic
HV generator
1)
Mask option
3.1
Analog Front End (AFE)
The AFE includes all circuits which are directly connected to the coil. It generates the IC’s power
supply and handles the bi-directional data communication with the reader. It consists of the fol-
lowing blocks:
• Rectifier to generate a DC supply voltage from the AC coil voltage
• Clock extractor
• Switchable load between Coil 1 and Coil 2 for data transmission from the tag to the reader
• Field gap detector for data transmission from the base station to the tag
• ESD protection circuitry
2
ATA5567
4874F–RFID–07/08
ATA5567
3.2
Data-rate Generator
The data rate is binary programmable to operate at any data rate between RF/2 and RF/128 or
equal to any of the fixed e5550/e5551 and T5554 bit rates (RF/8, RF/16, RF/32, RF/40, RF/50,
RF/64, RF/100, and RF/128).
3.3
Write Decoder
This function decodes the write gaps and verifies the validity of the data stream according to the
Atmel e555x write method (pulse interval encoding).
3.4
HV Generator
This on-chip charge pump circuit generates the high voltage required for programming of the
EEPROM.
3.5
DC Supply
Power is externally supplied to the IDIC via the two coil connections. The IC rectifies and regu-
lates this RF source and uses it to generate its supply voltage.
3.6
Power-On Reset (POR)
This circuit delays the IDIC functionality until an acceptable voltage threshold has been reached.
3.7
Clock Extraction
The clock extraction circuit uses the external RF signal as its internal clock source.
3.8
Controller
The control-logic module executes the following functions:
• Loads mode register with configuration data from EEPROM block 0 after power-on and also
during reading
• Controls memory access (read, write)
• Handles write data transmission and write error modes
The first two bits of the reader to tag data stream are the opcode, for example, write, direct
access, or reset.
In password mode, the 32 bits received after the opcode are compared with the password stored
in memory block 7.
3.9
Mode Register
The mode register stores the configuration data from the EEPROM block 0. It is continually
refreshed at the start of every block read and (re-)loaded after any POR event or reset com-
mand. On delivery, the mode register is preprogrammed with the value 0014 8000h which
corresponds to continuous read of block 0, Manchester coded, RF/64.
3
4874F–RFID–07/08
Figure 3-2.
Block 0 Configuration Mapping – e5550 Compatibility Mode
L
1 2
0 1
3 4
1 0
5 6
0 0
7 8
0 0
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
0 0
0
Data
Bit Rate
RF/8
RF/16
RF/32
0
1
Unlocked
Locked
RF/40
RF/50
RF/64
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
0
AOR
Modulation
PSK
CF
0
ST-sequence Terminator
PWD
Max
Block
0
0
POR delay
4874F–RFID–07/08
Lock Bit
Master Key
Note 1), 2)
0 0 RF/2
0 1 RF/4
1 0 RF/8
1 1 Res
0 0 0 0 0 Direct
0 0 0 0 1 PSK1
0 0 0 1 0 PSK2
0 0 0 1 1 PSK3
0 0 1 0 0 FSK1
0 0 1 0 1 FSK2
0 0 1 1 0 FSK1a
0 0 1 1 1 FSK2a
0 1 0 0 0 Manchester
1 0 0 0 0 Bi-phase ('50)
1 1 0 0 0 Reserved
RF/100 1 1 0
RF/128 1 1 1
1) If Master Key = 6 then test mode write commands are ignored
2) If Master Key < > 6 or 9 then extended function mode is disabled
3.10
Modulator
The modulator consists of data encoders for the following basic types of modulation:
Table 3-1.
Mode
FSK1a
(1)
FSK2a
(1)
FSK1
(1)
FSK2
(1)
PSK1
(2)
Types of e5550-compatible Modulation Modes
Direct Data Output
FSK/8-/5
FSK/8-/10
FSK/5-/8
FSK/10-/8
0 = RF/8;
0 = RF/8;
0 = RF/5;
0 = RF/10;
1 = RF/5
1 = RF/10
1 = RF/8
1 = RF/8
Phase change when input changes
Phase change on bit clock if input high
Phase change on rising edge of input
0 = falling edge, 1 = rising edge
1 creates an additional mid-bit change
1 = damping on, 0 = damping off
PSK2
(2)
PSK3
(2)
Manchester
Bi-phase
NRZ
Notes:
1. A common multiple of bit rate and FSK frequencies is recommended.
2. In PSK mode the selected data rate has to be an integer multiple of the PSK sub-carrier
frequency.
4
ATA5567
ATA5567
3.11
Memory
The memory is a 330-bit EEPROM, which is arranged in 10 blocks of 33 bits each. All 33 bits of
a block, including the lock bit, are programmed simultaneously.
Block 0 of page 0 contains the mode/configuration data, which is not transmitted during regu-
lar-read operations. Block 7 of page 0 may be used as a write protection password.
Bit 0 of every block is the lock bit for that block. Once locked, the block (including the lock bit
itself) is not re-programmable through the RF field.
Blocks 1 and 2 of page 1 contain traceability data and are transmitted with the modulation
parameters defined in the configuration register after the opcode “11” is issued by the reader
(see
Figure 4-6 on page 11).
These traceability data blocks are programmed and locked by
Atmel.
Figure 3-3.
Memory Map
0 1
Page 1
32
Traceability data
Traceability data
User data or password
User data
User data
User data
User data
User data
User data
Configuration data
Block 2
Block 1
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
Block 0
1
1
L
L
L
Page 0
L
L
L
L
L
32 bits
Not transmitted
3.12
Traceability Data Structure
Blocks 1 and 2 of page 1 contain the traceability data and are programmed and locked by Atmel
during production testing
(1)
. The most significant byte of block 1 is fixed to E0h, the allocation
class (ACL) as defined in ISO/IEC 15963-1. The second byte is therefore defined as Atmel
®
’s
manufacturer ID (15h). The following 8 bits are used as IC reference byte (ICR bits 47 to 40).
The 3 most significant bits define the IC version of the ATA5567, the foundry version, or both.
The lower 5 bits are by default reset (00) as the Atmel standard value. Other values may be
assigned, by request, to high volume customers as tag issuer identification.
The lower 40 bits of the data encode Atmel’s traceability information, and conform to a unique
numbering system. These 40 data bits are divided in two sub-groups, a 5-digit lot ID number,
and the binary wafer number (5 bits) concatenated with the sequential die number per wafer.
Note:
1. This is only valid for sawn wafer “DDB, DDT” delivery.
5
4874F–RFID–07/08
