Features
•
•
•
•
•
•
•
•
Contactless Read/Write Data Transmission
Sensor Input R
S
> 100 kΩ (Typical) => Data Stream Inverted
Radio Frequency f
RF
from 100 kHz to 150 kHz
e5550 Binary Compatible or ATA5570 Extended Mode
Small Size, Configurable for ISO/IEC 11784/785 Compatibility
7 x 32-bit EEPROM Data Memory Including 32-bit Password
Separate 64-bit Memory for Traceability Data
32-bit Configuration Register in EEPROM to Setup
– Data Rate
• RF/2 to RF/128, Binary Selectable or
• Fixed e5550 Data Rates
– Modulation/Coding
• FSK, PSK, Manchester, Bi-phase, NRZ
– Other Options
• Password Mode
• Maximum Block Feature
• Answer-On-Request (AOR) Mode
• Inverse Data Output
• Direct Access Mode
• Sequence Terminator(s)
• Write Protection (Through Lock-bit per Block)
• Fast Write Method (5 Kbps versus 2 Kbps)
• OTP Functionality
• POR Delay up to 67 ms
Multifunctional
330-bit
Read/Write RF
Sensor
Identification IC
ATA5570
Preliminary
1. Description
The ATA5570 is a contactless R/W
IDentification IC
(IDIC
®
) for applications in the
125 kHz frequency range. A single coil, connected to the chip, serves as the IC's
power supply and bi-directional communication interface. The antenna and chip
together form a transponder or tag.
The on-chip 330-bit EEPROM (10 blocks, 33 bits each) can be read and written block-
wise from a reader. Block 0 is reserved for setting the operation modes of the
ATA5570 tag. Block 7 may contain a password to prevent unauthorized writing.
Data is transmitted from the IDIC using load modulation. This is achieved by damping
the RF field with a resistive load between the two terminals COIL1 and COIL2. The IC
receives and decodes 100% amplitude-modulated (OOK) pulse-interval-encoded bit
streams from the base station or reader.
Rev. 4863A–RFID–07/05
2. System Block Diagram
Figure 2-1.
RFID System Using ATA5570 Tag
Transponder
Power
Reader
Baseor
station
Base station
Coil Interface
Controller
Memory
Data
ATA5570
3. Pin Configuration
Figure 3-1.
Pinning SO8
NC
COIL1
NC
SENS
1
2
3
4
8
7
6
5
NC
COIL2
NC
VSS
Table 3-1.
Pin
1
2
3
4
5
6
7
8
Pin Description
Symbol
NC
COIL1
NC
SENS
VSS
NC
COIL2
NC
Function
Not connected
Antenna pin 1
Not connected
Sensor input
Ground
Not connected
Antenna pin 2
Not connected
2
ATA5570 [Preliminary]
4863A–RFID–07/05
ATA5570 [Preliminary]
4. ATA5570 – Building Blocks
Figure 4-1.
Block Diagram
R
S
VSS
SENS
POR
Modulator
Analog front end
COIL1
C
R
Write
decoder
LR
Mode register
Memory
(264 bit
EEPROM)
Input register
Test logic
HV generator
Controller
COIL2
4.1
Analog Front End (AFE)
The AFE includes all circuits which are directly connected to the coil. It generates the IC’s power
supply and handles the bi-directional data communication with the reader. It consists of the fol-
lowing blocks:
• Rectifier to generate a DC supply voltage from the AC coil voltage
• Clock extractor
• Switchable load between COIL1 and COIL2 for data transmission from tag to the reader
• Field gap detector for data transmission from the base station to the tag
• ESD protection circuitry
4.2
Data-rate Generator
The data rate is binary programmable to operate at any data rate between RF/2 and RF/128 or
equal to any of the fixed e5550/e5551 and T5554 bit rates (RF/8, RF/16, RF/32, RF/40, RF/50,
RF/64, RF/100 and RF/128).
4.3
Write Decoder
This function decodes the write gaps and verifies the validity of the data stream according to the
Atmel e555x write method (pulse interval encoding).
Bit-rate
generator
3
4863A–RFID–07/05
4.4
HV Generator
This on-chip charge-pump circuit generates the high voltage required for programming of the
EEPROM.
4.5
DC Supply
Power is externally supplied to the IDIC via the two coil connections. The IC rectifies and regu-
lates this RF source and uses it to generate its supply voltage.
4.6
Power-On Reset (POR)
This circuit delays the IDIC functionality until an acceptable voltage threshold has been reached.
4.7
Clock Extraction
The clock extraction circuit uses the external RF signal as its internal clock source.
4.8
Controller
The control-logic module executes the following functions:
• Load-mode register with configuration data from EEPROM block 0 after power-on and also
during reading
• Control memory access (read, write)
• Handle write data transmission and write error modes
• The first two bits of the reader-to-tag data stream are the opcode, e.g., write, direct access or
reset
• In password mode, the 32 bits received after the opcode are compared with the password
stored in memory block 7
4.9
Mode Register
The mode register stores the configuration data from the EEPROM block 0. It is continually
refreshed at the start of every block read and (re-)loaded after any POR event or reset com-
mand. On delivery, the mode register is preprogrammed with the value 0014 8000h which
corresponds to continuous read of block 0, Manchester coded, RF/64.
4
ATA5570 [Preliminary]
4863A–RFID–07/05
ATA5570 [Preliminary]
Figure 4-2.
L
1
1
Block 0 Configuration Mapping – e5550 Compatibility Mode
2
0
3 4
0
1
5
0
6
0
7 8
0
0
n5 n4 n3 n2 n1 n0
Data Bit Rate
RF/(2n + 2)
Direct
PSK1
9 10 11 12
13 14 15 16 17 18 19 20
1
X-Mode
PWD
AOR
OTP
Modulation
PSK-
CF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
1
1
0
1
0
1
MAX-
BLOCK
21 22 23 24 25 26 27 28 29 30 31 32
Master Key
Lock Bit
Note 1), 2)
ST-Sequence Terminator
Fast Write
RF/2
RF/4
RF/8
Res.
0
1
Unlocked
Locked
PSK2
PSK3
FSK1
FSK2
Mode-Defeat 1 0
Mode-Defeat 2 0
Manchester
Biphase ('50)
Biphase ('57)
0
1
1
1) If Master Key = 6 and bit 15 set, then test-mode access is disabled and extended mode is active
2) If Master Key = 9 and bit 15 set, then extended mode is enabled
4.10
Modulator
The modulator consists of data encoders for the following basic types of modulation:
Table 4-1.
Types of e5550-compatible Modulation Modes
Encoding
FSK/8, FSK/5
FSK/8, FSK/10
FSK/5, FSK/8
FSK/10, FSK/8
“0” = RF/8;
“0” = RF/8;
“0” = RF/5;
“0” = RF/10;
“1” = RF/5
“1” = RF/10
“1” = RF/8
“1” = RF/8
Mode
Direct Data Output
FSK1a
(1)
FSK2a
(1)
FSK1
(1)
FSK2
(1)
PSK1
(2)
PSK2
(2)
PSK3
(2)
Manchester
Bi-phase
NRZ
Notes:
Phase change when input changes
Phase change on bit clock if input high
Phase change on rising edge of input
“0” = falling edge, “1” = rising edge
“1” creates an additional mid-bit change
“1” = damping on, “0” = damping off
1. A common multiple of bit rate and FSK frequencies is recommended.
2. In PSK mode the selected data rate has to be an integer multiple of the PSK sub-carrier
frequency.
Inverse Data
POR Delay
5
4863A–RFID–07/05
