Features
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High-density, High-performance Fully CMOS, Electrically-erasable Complex
Programmable Logic Device
– 128 Macrocells
– 5.0 ns Pin-to-pin Propagation Delay
– Registered Operation up to 333 MHz
– Enhanced Routing Resources
– Optimized for 3.3V Operation
– On-chip Voltage Regulator
– 2 I/O Banks to Facilitate Multi-voltage I/O Operation: 1.5V, 1.8V, 2.5V, 3.3V
– SSTL2 and SSTL3 I/O Standards
In-System Programming (ISP) Supported
– ISP Using IEEE 1532 (JTAG) Interface
– IEEE 1149.1 JTAG Boundary Scan Test
Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– 5 Product Terms per Macrocell, Expandable up to 40
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate with Low Output Drive
– Programmable Open Collector Output Option
– Maximum Logic Utilization by Burying a Register with a Combinatorial Output and
Vice Versa
Fully Green (RoHS Compliant)
As Low As 70 µA Standby Current
Power Saving Option During Operation Using PD1 and PD2 Pins
Programmable Pin-keeper Option on Inputs and I/Os
Programmable Schmitt Trigger Input Option on Input and I/O Pins
Programmable Input and I/O Pull-up Option
Unused I/O Pins Can Be Configured as Ground (Optional)
Available in Commercial and Industrial Temperature Ranges
Available in 100-lead TQFP and 132-ball CBGA
Advanced Digital CMOS Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
Security Fuse Feature
Hot-Socketing Supported
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High-
performance
CPLD
ATF1508RE
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3682A–PLD–10/08
Enhanced Features
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Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
Outputs Can Be Configured for High or Low Drive
Combinatorial Output with Registered Feedback and Vice Versa within each Macrocell
Three Global Clock Pins
Fast Registered Input from Product Term
Pull-up Option on TMS and TDI JTAG Pins
OTF (On-the-Fly) Reconfiguration Mode
DRA (Direct Reconfiguration Access)
1. Description
The ATF1508RE is a high-performance, high-density complex programmable logic device
(CPLD) that utilizes Atmel’s proven electrically-erasable memory technology. With 128 logic
macrocells and up to 84 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and
classic PLDs. The ATF1508RE’s enhanced routing switch matrices increase usable gate count
and the odds of successful pin-locked design modifications.
The ATF1508RE has up to 80 bi-directional I/O pins, four dedicated input pins, 1 internal voltage
regulator supply input pin (VCCIRI), 6 I/O VCC pins (VCCIOA and VCCIOB), 8 ground pins
(GND and 1 internal voltage regulator output pin (VCCIR0). Each dedicated input pin can also
serve as a global control signal, register clock, register reset or output enable. Each of these
control signals can be selected for use individually within each macrocell.
Figures 1-1 and 1-2
show the pin assignments for the 100-lead TQFP and 132-ball CBGA packages, respectively.
2
ATF1508RE
3682A–PLD–10/08
ATF1508RE
Figure 1-1.
100-lead TQFP Top View
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCIRI
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIOB
I/O
I/O
I/O
I/O
I/O
I/O
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
I/O/PD1
I/O
VCCIOA
I/O/TDI
I/O
I/O
I/O
I/O
I/O
I/O
GND
VREFA / I/O
I/O
I/O
I/O/TMS
I/O
I/O
VCCIOA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
33
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
I/O
I/O
VCCIOB
I/O
I/O
I/O
I/O/TCK
I/O
I/O / VREFB
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIOB
Note:
VCCIRO (P39 for 100 TQFP) needs to be left floating and used for coupling (use 2.2 µF/or 4.7 µF X7R chip CAP and 470 pF
NPO chip CAP.
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIOA
I/O
I/O
I/O
GND
VCCIRO
I/O
I/O/PD2
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
3
3682A–PLD–10/08
Figure 1-2.
132-CBGA Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
I/O
VCCIRI I/GCLR
I/O
I/O
NC
VCCIOB
NC
GND
I/O
I/O
I/O
NC
VCCIOB
B
I/O
I/O
GND
I/O
I/O
NC
NC
NC
I/O/TDO
NC
I/O
I/O
NC
GND
C
I/O
I/OE1
I/OE2/ VCCIOB
GCLK2
NC
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
NC
NC
D
I/O
I/O
I/O
I/O
I/O
E
I/O
I/O
I/O
I/O
I/O
GND
F
I/O/PD1
I/O
I/O
I/O
I/O
I/O
G
I/O
I/O
I/O
I/O/PD2
I/O
VCCIOA
H
I/O/VREFA
I/O
I/O
I/O
I/O
GND
J
I/O
I/O
VCCIOA
I/O
I/O
GND
K
I/O
GND
I/O
VCCIRI
I/O
I/O
L
NC
I/GCLK1
NC
I/O
I/O/VREFB
I/O
M
NC
NC
I/O
I/O
I/O
I/O
NC
I/O
I/O/TDI I/O/TCK
I/O
NC
NC
NC
N
GND
NC
I/O
NC
I/O
I/O
NC
NC
GND
I/O/TMS
I/O
GND
I/O
I/O
P
VCCIRO
I/O
I/O
GND
I/O
NC
VCCIOA
NC
I/O
I/O
I/O
I/O
VCCIOA
I/O
Notes:
1. The 132-ball CBGA package is 8 x 8 x 1.2 mm in size with 0.5 mm ball spacing.
2. VCCIRO (P1 for 132 CBGA) needs to be left floating and connect to coupling CAP (use 2.2 µF/or 4.7 µF X7R chip CAP and
470PF or 1 nF NPO chip CAP.
4
ATF1508RE
3682A–PLD–10/08
ATF1508RE
Figure 1-3.
Block Diagram
10
16
10
5
3682A–PLD–10/08
