Features
•
16-channel GPS Correlator
– 8192 Search Bins with GPS Acquisition Accelerator
– Accuracy: 2.5m CEP (2D, Stand Alone)
– Time to First Fix: 34s (Cold Start)
– Acquisition Sensitivity: –142 dBm (Cold Start, With External LNA)
– Tracking Sensitivity: –158 dBm (With External LNA)
Utilizes the ARM7TDMI
®
ARM
®
Thumb
®
Processor Core
– High-performance 32-bit RISC Architecture
– EmbeddedICE
™
(In-Circuit Emulation)
128 Kbytes Internal RAM
384 Kbytes Internal ROM with u-blox GPS Firmware SuperSense
®
1.5-bit ADC On-chip
Single IF Architecture
2 External Interrupts
24 User-programmable I/O Lines
1 USB Device Port
– Universal Serial Bus (USB) 2.0 Full-speed Device
– Embedded USB V2.0 Full-speed Transceiver
2 USARTs
Master/Slave SPI Interface
– 4 External Slave Chip Selects
Programmable Watchdog Timer
Advanced Power Management Controller (APMC)
– Geared Master Clock to Reduce Power Consumption
– Sleep State with Disabled Master Clock
– Hibernate State with 32.768 kHz Master Clock
Real Time Clock (RTC)
1.8V to 3.3V User-definable IO Voltage for Several GPIOs with 5V Tolerance
4 KBytes of Battery Backup Memory
7 mm
×
10 mm 96 Pin BGA Package, 0.8 mm Pitch, Pb-free, RoHS-compliant
•
•
•
•
•
•
•
•
ANTARIS4
Single-chip
GPS Receiver
SuperSense
ATR0635P1
Automotive
•
•
•
•
•
•
•
•
Benefits
•
•
•
•
•
•
•
Fully Integrated Design With Low BOM
No External Flash Memory Required
Supports NMEA
®
, UBX Binary and RTCM Protocol for DGPS
Supports SBAS (WAAS, EGNOS, MSAS)
Up to 4 Hz Update Rate
Supports A-GPS (Aiding)
Excellent Noise Performance
4979D–GPS–06/08
1. Description
The ATR0635P1 is a low-power, single-chip GPS receiver, especially designed to meet the
requirements of mobile applications. It is based on Atmel
®
’s ANTARIS
®
4 technology and inte-
grates an RF front-end, filtering, and a baseband processor in a single, tiny 7 mm
×
10 mm
96 pin BGA package. Providing excellent RF performance with low noise figure and low power
consumption.
Due to the fully integrated design, just an RF SAW filter, a GPS TCXO and blocking capacitors
are required to realize a stand-alone GPS functionality.
The ATR0635P1 includes a complete GPS firmware, licensed from u-blox AG, which performs
the GPS operation, including tracking, acquisition, navigation and position data output. For nor-
mal PVT (Position/Velocity/Time) applications, there is no need for external Flash- or
ROM-memory.
The firmware supports e.g. the NMEA protocol (2.1 and 2.3), a binary protocol for PVT data,
configuration and debugging, the RTCM protocol for DGPS, SBAS (WAAS, EGNOS and MSAS)
and A-GPS (aiding). It is also possible to store the configuration settings in an optional external
EEPROM.
Due to the integrated ARM7TDMI processor and an intelligent radio architecture, the
ATR0635P1 operates in a complete autonomous mode, utilizing on chip AGC in closed loop
operation.
For maximum performance, we recommend to use the ATR0635P1 together with a low noise
amplifier (e.g. ATR0610).
The ATR0635P1 supports assisted GPS.
2
ATR0635P1
4979D–GPS–06/08
ATR0635P1
2. Architectural Overview
2.1
Block Diagram
ATR0635P1 Block Diagram
PUXTO
PURF
VDD18
VDDIO
VDD_USB
VDIG
VCC1
VCC2
VBP
VBAT18
VBAT
LDOBAT_IN
LDO_OUT
LDO_IN
LDO_EN
Figure 2-1.
Power Supply Manager/
PMSS/Logic
AGCO
EGC
SDI
TEST
MO
1
A
RF
NRF
VCO
PLL
D
SIGHI
A
D
SIGLO
XTO
NXTO
CLK23
XTO
X
NX
GPS
Accelerator
APB
RF_ON
Advanced
Power
Manage-
ment
Controller
XT_IN
XT_OUT
SMD
Generator
SRAM
RTC
NSHDN
NSLEEP
P20/TIMEPULSE
P29/GPSMODE12
P27/GPSMODE11
P26/GPSMODE10
P24/GPSMODE8
P23/GPSMODE7
P19/GPSMODE6
P17/GPSMODE5
P13/GPSMODE3
P12/GPSMODE2
P1/GPSMODE0
P14/NAADET1
PIO2
PIO2
Controller
SPI
Timer
Counter
GPS
Correlators
USART2
Special
Function
PIO2
P21/TXD2
P22/RXD2
Advanced
Interrupt
Controller
USART1
P25/NAADET0
P15/ANTON
P0/NANTSHORT
P18/TXD1
P31/RXD1
P9/EXTINT0
USB
Transceiver
Watchdog
P16/NEEPROM
USB_DP
USB_DM
B
R
I
D
G
E
USB
ASB
P8/STATUSLED
P30/AGCOUT0
P2/BOOT_MODE
Interface to
Off-Chip
Memory
(EBI)
ARM7TDMI
Embedded
ICE
DBG_EN
NTRST
TDI
TDO
TCK
TMS
JTAG
Reset
Controller
SRAM
128K
ROM
384K
PDC2
NRESET
3
4979D–GPS–06/08
2.2
General Description
The ATR0635P1 has been designed especially for mobile applications. It provides high isolation
between GPS and cellular bands, as well as very low power consumption.
ATR0635P1 is based on the successful ANTARIS4 technology which includes the ANTARIS
high performance SuperSense software in ROM, developed by u-blox AG, Switzerland. ANTA-
RIS provides a proven navigation engine which is used in high-end car navigation systems,
automatic vehicle location (AVL), security and surveying systems, traffic control, road pricing,
and speed camera detectors, and provides location-based services (LBS) worldwide.
The ANTARIS4 chipset has a very low power consumption and comes with a very low BoM for
the passive components. Also, as the high performance software SuperSense is available in
ROM, no external flash memory is needed.
The L1 input signal (f
RF
) is a Direct Sequence Spread Spectrum (DSSS) signal with a center fre-
quency of 1575.42 MHz. The digital modulation scheme is Bi-Phase-Shift-Keying (BPSK) with a
chip rate of 1.023 Mbps.
2.3
PMSS Logic
The power management, startup and shutdown (PMSS) logic ensures reliable operation within
the recommended operating conditions. The external power control signals PUrf and PUxto are
passed through Schmitt trigger inputs to eliminate voltage ripple and prevent undesired behavior
during start-up and shut-down. Digital and analog supply voltages are analyzed by a monitoring
circuit, enabling the startup of the IC only when it is within a safe operating range.
2.4
VCO/PLL
The frequency synthesizer features a balanced VCO and a fully integrated loop filter, thus no
external components are required. The VCO combines very good phase noise behavior and
excellent spurious suppression.The relation between the reference frequency (f
TCXO
) and the
VCO center frequency (f
TCXO
) is given by:
f
VCO
= f
TCXO
×
64 = 23.104 MHz
×
64 = 1478.656 MHz.
2.5
RF Mixer/Image Filter
Combined with the antenna, an external LNA provides a first band-path filtering of the signal.
Atmel’s ATR0610 is recommended for the LNA due to its low noise figure, high linearity and low
power consumption. The output of the LNA drives a SAW filter, which provides image rejection
for the mixer and the required isolation to all GSM bands. The output of the SAW filter is fed into
a highly linear mixer with high conversion gain and excellent noise performance.
2.6
VGA/AGC
The on-chip automatic gain control (AGC) stage sets the gain of the VGA in order to optimally
load the input of the following analog-to-digital converter. The AGC control loop can be selected
for on-chip closed-loop operation or for baseband controlled gain mode.
4
ATR0635P1
4979D–GPS–06/08
ATR0635P1
2.7
Analog-to-digital Converter
The analog-to-digital converter stage has a total resolution of 1.5 bits. It comprises balanced
comparators and a sub-sampling unit, clocked by the reference frequency (f
TCXO
). The fre-
quency spectrum of the digital output signal (f
OUT
), present at the data outputs SIGLO and
SIGH1, is 4.348 MHz.
2.8
Baseband
The GPS baseband core includes a 16-channel correlator and is based on an ARM7TDMI ARM
processor core with very low power consumption. It has a high-performance 32 bit RISC archi-
tecture, uses a high-density 16-bit instruction set. The ARM standard In-Circuit Emulation debug
interface is supported via the JTAG/ICE port of the ATR0635P1.
The ATR0635P1 architecture consists of two main buses, the Advanced System Bus (ASB) and
the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It inter-
faces the processor with the on-chip 32-bit memories and the external memories and devices by
means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip periph-
erals and is optimized for low power consumption. The AMBA
™
Bridge provides an interface
between the ASB and the APB.
An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip USARTs/SPI
and the on- and off-chip memories without processor intervention. Most importantly, the PDC2
removes the processor interrupt handling overhead and significantly reduces the number of
clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes without
reprogramming the starting address. As a result, the performance of the microcontroller is
increased and the power consumption reduced.
All of the external signals of the on-chip peripherals are under the control of the Parallel I/O Con-
troller (PIO2). The PIO2 Controller can be programmed to insert an input filter on each pin or
generate an interrupt on a signal change. After reset, the user must carefully program the PIO2
Controller in order to define which peripheral signals are connected with off-chip logic.
The ATR0635P1 features a Programmable Watchdog Timer.
An Advanced Power Management Controller (APMC) allows for the peripherals to be deacti-
vated individually. Automatic master clock gearing reduces power consumption. A Sleep Mode
is available with disabled 23.104 MHz master clock, as well as a Back-up Mode operating
32.768 kHz master clock.
A 32.768 kHz Real Time Clock (RTC), together with a buit-in battery back-up SRAM, allows for
storage of Almanac, Ephemeris, software configurations to make quick hot- and warm starts.
The ATR0635P1 includes the full high performance firmware (SuperSense), licensed from
u-blox AG, Switzerland. Features of the ROM firmware are described in a software documenta-
tion available from u-blox AG, Switzerland.
5
4979D–GPS–06/08
