Features
•
Core
– ARM
®
Cortex
®
-M3 revision 2.0 running at up to 48 MHz
– Thumb
®
-2 instruction
– 24-bit SysTick Counter
– Nested Vector Interrupt Controller
Pin-to-pin compatible with SAM7S legacy products (48- and 64-pin versions) and
SAM3S (48-, 64- and 100-pin versions)
Memories
– From 16 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,
single plane
– From 4 to 24 Kbytes embedded SRAM
– 16 Kbytes ROM with embedded bootloader routines (UART) and IAP routines
System
– Embedded voltage regulator for single supply operation
– Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe
operation
– Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure
Detection and optional low power 32.768 kHz for RTC or device clock
– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default
frequency for device startup. In-application trimming access for frequency
adjustment
– Slow Clock Internal RC oscillator as permanent low-power mode device clock
– One PLL up to 130 MHz for device clock
– Up to 10 peripheral DMA (PDC) channels
Low Power Modes
– Sleep and Backup modes, down to 3 µA in Backup mode
– Ultra low power RTC
Peripherals
– Up to 2 USARTs with RS-485 and SPI mode support. One USART (USART0) has
ISO7816, IrDA® and PDC support in addition
– Two 2-wire UARTs
– 2 Two Wire Interface (I2C compatible), 1 SPI
– Up to 6 Three-Channel 16-bit Timer/Counter with capture, waveform, compare and
PWM mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for
Stepper Motor
– 4-channel 16-bit PWM
– 32-bit Real-time Timer and RTC with calendar and alarm features
– Up to 16 channels, 384 KSPS 10-bit ADC
– One 500 KSPS 10-bit DAC
I/O
– Up to 79 I/O lines with external interrupt capability (edge or level sensitivity),
debouncing, glitch filtering and on-die Series Resistor Termination
– Three 32-bit Parallel Input/Output Controllers
Packages
– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm/100-ball TFBGA, 9 x 9 mm, pitch 0.8 mm
– 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm/64-pad QFN 9x9 mm, pitch 0.5 mm
– 48-lead LQFP, 7 x 7 mm, pitch 0.5 mm/48-pad QFN 7x7 mm, pitch 0.5 mm
•
•
•
AT91SAM
ARM-based
Flash MCU
ATSAM3N Series
•
•
•
•
11011B–ATARM–21-Feb-12
1. SAM3N Description
Atmel's SAM3N series is a member of a family of Flash microcontrollers based on the high per-
formance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 48 MHz
and features up to 256 Kbytes of Flash and up to 24 Kbytes of SRAM. The peripheral set
includes 2x USARTs, 2x UARTs, 2x TWIs, 3x SPI, as well as 1 PWM timer, 6x general purpose
16-bit timers, an RTC, a 10-bit ADC and a 10-bit DAC.
The SAM3N series is ready for capacitive touch thanks to the QTouch library, offering an easy
way to implement buttons, wheels and sliders.
The SAM3N device is an entry-level general purpose microcontroller. That makes the SAM3N
the ideal starting point to move from 8- /16-bit to 32-bit microcontrollers.
It operates from 1.62V to 3.6V and is available in 48-pin, 64-pin and 100-pin QFP, 48-pin and
64-pin QFN, and 100-pin BGA packages.
The SAM3N series is the ideal migration path from the SAM3S for applications that require a
reduced BOM cost. The SAM3N series is pin-to-pin compatible with the SAM3S series. Its
aggressive price point and high level of integration pushes its scope of use far into cost-sensi-
tive, high-volume applications.
2
SAM3N
11011B–ATARM–21-Feb-12
SAM3N
1.1
Configuration Summary
The SAM3N4/2/1/0/00 differ in memory size, package and features list.
Table 1-1
summarizes
the configurations of the 9 devices.
Table 1-1.
Device
SAM3N4A
SAM3N4B
SAM3N4C
SAM3N2A
SAM3N2B
SAM3N2C
SAM3N1A
SAM3N1B
SAM3N1C
SAM3N0A
SAM3N0B
SAM3N0C
SAM3N00A
SAM3N00B
Notes:
Configuration Summary
Flash
256 Kbytes
256 Kbytes
256 Kbytes
128 Kbytes
128 Kbytes
128 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
16 Kbytes
16 Kbytes
SRAM
24 Kbytes
24 Kbytes
24 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
4 KBytes
4 KBytes
Package
LQFP48
QFN48
LQFP64
QFN64
LQFP100
BGA100
LQFP48
QFN48
LQFP64
QFN64
LQFP100
BGA100
LQFP48
QFN48
LQFP64
QFN64
LQFP100
BGA100
LQFP48
QFN48
LQFP64
QFN64
LQFP100
BGA100
LQFP48
QFN48
LQFP64
QFN64
Number
of PIOs
34
47
79
34
47
79
34
47
79
34
47
79
34
47
ADC
8 channels
10 channels
16 channels
8 channels
10 channels
16 channels
8 channels
10 channels
16 channels
8 channels
10 channels
16 channels
8 channels
10 channels
Timer
6
(1)
6
(2)
6
6
(1)
6(
(2)
6
6
(1)
6
(2)
6
6
(1)
6
(2)
6
6
(1)
6
(2)
PDC
Channels
8
10
10
8
10
10
8
10
10
8
10
10
8
10
USART
1
2
2
1
2
2
1
2
2
1
2
2
1
2
DAC
_
1
1
_
1
1
_
1
1
_
1
1
_
1
1. Only two TC channels are accessible through the PIO.
2. Only three TC channels are accessible through the PIO.
3
11011B–ATARM–21-Feb-12
2. SAM3N Block Diagram
Figure 2-1.
SAM3N 100-pin version Block Diagram
TD
TDI
O
TM /TR
S
A
TC /
S
W CE
K/ D
S
W
S
W IO O
CL
K
S
E
L
VD
DI
N
System
Controller
TST
PCK0-PCK2
Voltage
Regulator
JTAG &
Serial
Wire
PMC
XIN
XOUT
OSC
3-20
MHz
WDT
RC OSC
12/8/4 MHz
In-Circuit Emul tor
a
SM
SUPC
XIN32
XOUT32
ERASE
24-bit
N
SysTick
Counter
V
Cortex-M3 Processor
I
Fmax 48 MHz
C
I/D
S
FLASH
256 KBytes
128 KBytes
64 KBytes
32
KBytes
16 KBytes
24 KBytes
16 KBytes
8
KBytes
4 KBytes
VD
DO
JT
AG
SRAM
UT
ROM
16 KBytes
OSC
32k
RC
32k
PLL
RTT
RTC
POR
VDDIO
NRST
3-
layer AHB Bus Matrix Fmax 48 MHz
RSTC
Peripheral
Bridge
PIOA
PIOB
PIOC
VDDCORE
URXD0
UTXD0
URXD1
UTXD1
UART0
UART1
PDC
Timer Counter A
TC[0..2]
TCLK[0:2]
TIOA[0:2]
TIOB[0:2]
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
USART0
PDC
Timer Counter B
TC[3..5]
TCLK[3:5]
TIOA[3:5]
TIOB[3:5]
USART1
PDC
SPI
PWM[0:3]
PWM
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOS
SPCK
TWCK0
TWD0
ADTRG
AD[0..15]
ADVREF
DAC0
DATRG
PDC
10-bit ADC
PDC
TWI0
TWI1
10-bit DAC
PDC
TWCK1
TWD1
4
SAM3N
11011B–ATARM–21-Feb-12
SAM3N
Figure 2-2.
SAM3N 64-pin version Block Diagram
TD
TDI
O
TM /TR
S
A
TC /
S
W CE
K/ D
S
W
S
W IO O
CL
K
S
E
L
VD
DI
N
System
Controller
TST
PCK0-PCK2
Voltage
Regulator
JTAG &
Serial
Wire
PMC
XIN
XOUT
OSC
3-20
MHz
In-Circuit Emulator
WDT
RC OSC
12/8/4 MHz
SM
SUPC
XIN32
XOUT32
ERASE
24-bit
N
SysTick
Counter
V
Cortex-M3 Processor
I
Fmax 48 MHz
C
I/D
S
FLASH
256 KBytes
128 KBytes
64 KBytes
32
KBytes
16 KBytes
24 KBytes
16 KBytes
8
KBytes
4 KBytes
VD
DO
JT
AG
SRAM
UT
ROM
16 KBytes
OSC
32k
RC
32k
PLL
RTT
RTC
POR
VDDIO
NRST
3-layer
AHB Bus Matrix Fmax 48 MHz
48 MHz
3-
layer AHB Bus Matrix Fmax
RSTC
Peripheral
Bridge
PIOA
PIOB
VDDCORE
URXD0
UTXD0
URXD1
UTXD1
UART0
UART1
PDC
Timer Counter A
TC[0..2]
TCLK[0:2]
TIOA[0:2]
TIOB[0:2]
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
USART0
PDC
Timer Counter B
TC[3..5]
USART1
PDC
SPI
PWM[0:3]
PWM
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOS
SPCK
TWCK0
TWD0
ADTRG
AD[0..9]
ADVREF
DAC0
DATRG
PDC
10-bit ADC
PDC
TWI0
TWI1
10-bit DAC
PDC
TWCK1
TWD1
5
11011B–ATARM–21-Feb-12
微控制器 MCU
