ARIZONA MICROTEK, INC.
AZ12000, AZ12001
Phase-Locked Loop Clock Generator
FEATURES
•
•
•
•
•
•
•
•
•
PECL (AZ12000) or LVDS
(AZ12001) Outputs
Operating Range 3.0V to 5.5V
Internal Crystal Oscillator Driver
Internal Edge-Matching
Phase/Frequency Detector
Internal Charge-Pump and
Integrator Amplifier
Internal or External VCO
Divide by 4, 8, 16, 32
RF Bipolar Design for Low Phase
Noise
Available in a 4x4mm MLP Package
PACKAGE
MLP 24 (4x4)
MLP 24 (4x4)
DIE
DIE
1
2
3
PACKAGE AVAILABILITY
PART NO.
AZ12000K
AZ12001K
AZ12000XP
AZ12001XP
MARKING
AZ12000
<Date Code>
AZ12001
<Date Code>
N/A
N/A
NOTES
1,2
1,2
3
3
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
Date code format: “YY” for year followed by “WW” for week.
Waffle Pack
DESCRIPTION
The AZ12000/AZ12001 contains all of the functional elements necessary to implement a Phase-Locked Loop
for clock multiplication at frequencies up to 800 MHz. A reference crystal oscillator driver operates at frequencies
up to 200 MHz providing support for 4 times multiplication. The dynamic properties of the PLL are under the
control of the user through selection of the desired external components.
BLOCK DIAGRAM
T UOT NI
Q
T UPT UO
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LESO CV
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REFFUB
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Ω
1630 S. STAPLEY DR., SUITE 127
•
MESA, ARIZONA 85204
•
USA
•
(480) 962-5881
•
FAX (480) 890-2541
www.azmicrotek.com
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V
AZ12000
AZ12001
CC
V
CC
V
Bottom Center pad may be left open or tied to V
EE
.
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
V
CC
V
I
I
OUT
T
A
T
STG
Characteristic
Power Supply
(V
EE
= GND)
Input Voltage
(V
EE
= GND)
— Continuous
ECL/PECL Output Current
— Surge
Operating Temperature Range
Storage Temperature Range
Rating
0 to +6.0
0 to +6.0
40
80
-40 to +85
-65 to +150
Unit
Vdc
Vdc
mA
°C
°C
January 2005 * REV - 3
www.azmicrotek.com
2
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2SD
EE
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AZ12000
AZ12001
AZ12000 FUNCTIONAL PIN DESCRIPTIONS
Pin No
Pin Name
Functional Description
Reference Crystal Resonator Input
This pin includes an on-chip 470
Ω
pull
REFIN
down resistor to V
BB
. The input from the resonator circuit should be AC
coupled.
Crystal Resonator Output Drive
This pin is an inverted and amplified version
of the signal on the REFIN pin. The gain from REFIN to REFOUT is
¯¯¯¯¯¯¯
REFOUT
¯¯¯¯¯¯¯
approximately 20. The IC includes a 4 ma on-chip current source. If more
current is needed, the REFOUT pin may be connected to V
EE
through a resistor
¯¯¯¯¯¯¯
to provide up to 8 ma additional current.
Charge Pump Reference Output
The pin voltage is nominally 1.2 volts below
CPREF
V
CC
. If an external integrator is used, CPREF should be connected to the
integrator reference input through a bias current cancellation network.
Charge Pump Output
The charge pump output voltage is V(CPREF)
±0.3V
during a phase correction pulse. When there is no correction pulse the output
CPOUT
goes high impedance. If an external integrator is used, CPOUT should be
connected to the input integrator resistor.
Charge Pump Polarity
Logic LOW on this pin causes CPOUT to go low
when the VCO frequency is too low, and go high when the VCO frequency is
too high. Logic HIGH on this pin causes CPOUT to go low when the VCO
CPPOL
frequency is too high, and go high when the VCO frequency is too low. This
pin should be LOW when the internal VCO is used.
If this pin is left open it is pulled to the HIGH condition.
Integrator Reference Input
This pin should be connected to CPREF through a
bias current cancellation network
Integrator Summing Junction
This pin is the summing junction for the
integrator amplifier
Integrator Output
Internal/External VCO Select
Logic HIGH on this pin enables the internal
VCO. Logic LOW on this pin disables the internal VCO and allows use of the
EXTVCO inputs.
If this pin is left open it is pulled to the HIGH condition.
VCO Tank
The tank components connect between this pin and V
CC
.
External VCO Input
The external VCO input pins should be driven
differentially for best performance.
Divide Select
VCO divide ratios are selected as shown:
DS1
Ratio
DS2
LOW
LOW
÷4
LOW
HIGH
÷8
÷16
HIGH
LOW
HIGH
HIGH
÷32
If the pins are left open they are pulled to the HIGH condition.
Clock Output
These pins are the main (multiplied) clock output.
No Connect
This pin is used during factory test. It mist be left open.
Reference Voltage Output
This pin is used to bias the REFIN signal. It must
be bypassed externally to the VEE pins with a 0.01
µF
capacitor.
Positive Supply
+3.0 to +5.5 V for PECL mode, Ground for ECL mode.
VCO Positive Supply
+3.0 to +5.5 V for PECL mode, Ground for ECL mode.
Negative Supply
Ground for PECL mode, –3.0 to –5.5 V for ECL mode.
Logic Level
ECL/PECL
CMOS/TTL
compatible
INTREF
INTSUM
INTOUT
VCOSEL
CMOS/TTL
compatible
TANK
EXTVCO
EXTVCO
¯¯¯¯¯¯¯¯
ECL/PECL
DS2
DS1
CMOS/TTL
compatible
Q
Q
¯
N/C
V
BB
V
CC
VCOV
CC
V
EE
ECL/PECL
January 2005 * REV - 3
www.azmicrotek.com
3
AZ12000
AZ12001
AZ12001 FUNCTIONAL PIN DESCRIPTIONS
Pin No
Pin Name
Functional Description
Reference Crystal Resonator Input
This pin includes an on-chip 470
Ω
pull
REFIN
down resistor to V
BB
. The input from the resonator circuit should be AC
coupled.
Crystal Resonator Output Drive
This pin is an inverted and amplified version
of the signal on the REFIN pin. The gain from REFIN to REFOUT is
¯¯¯¯¯¯¯
REFOUT
¯¯¯¯¯¯¯
approximately 20. The IC includes a 4 ma on-chip current source. If more
current is needed, the REFOUT pin may be connected to V
EE
through a resistor
¯¯¯¯¯¯¯
to provide up to 8 ma additional current.
Charge Pump Reference Output
The pin voltage is nominally 1.2 volts below
CPREF
V
CC
. If an external integrator is used, CPREF should be connected to the
integrator reference input through a bias current cancellation network.
Charge Pump Output
The charge pump output voltage is V(CPREF)
±0.3V
during a phase correction pulse. When there is no correction pulse the output
CPOUT
goes high impedance. If an external integrator is used, CPOUT should be
connected to the input integrator resistor.
Charge Pump Polarity
Logic LOW on this pin causes CPOUT to go low
when the VCO frequency is too low, and go high when the VCO frequency is
too high. Logic HIGH on this pin causes CPOUT to go low when the VCO
CPPOL
frequency is too high, and go high when the VCO frequency is too low. This
pin should be LOW when the internal VCO is used.
If this pin is left open it is pulled to the HIGH condition.
Integrator Reference Input
This pin should be connected to CPREF through a
bias current cancellation network
Integrator Summing Junction
This pin is the summing junction for the
integrator amplifier
Integrator Output
Internal/External VCO Select
Logic HIGH on this pin enables the internal
VCO. Logic LOW on this pin disables the internal VCO and allows use of the
EXTVCO inputs.
If this pin is left open it is pulled to the HIGH condition.
VCO Tank
The tank components connect between this pin and V
CC
.
External VCO Input
The external VCO input pins should be driven
differentially for best performance.
Divide Select
VCO divide ratios are selected as shown:
DS1
Ratio
DS2
LOW
LOW
÷4
LOW
HIGH
÷8
÷16
HIGH
LOW
HIGH
HIGH
÷32
If the pins are left open they are pulled to the HIGH condition.
Clock Output
These pins are the main (multiplied) clock output.
No Connect
This pin is used during factory test. It must be left open.
Reference Voltage Output
This pin is used to bias the REFIN signal. It must
be bypassed externally to the VEE pins with a 0.01
µF
capacitor.
Positive Supply
+3.0 to +5.5 V
VCO Positive Supply
+3.0 to +5.5 V
Negative Supply
Ground
Logic Level
PECL
CMOS/TTL
compatible
INTREF
INTSUM
INTOUT
VCOSEL
CMOS/TTL
compatible
TANK
EXTVCO
EXTVCO
¯¯¯¯¯¯¯¯
PECL
DS2
DS1
CMOS/TTL
Compatible
Q
Q
¯
N/C
V
BB
V
CC
VCOV
CC
V
EE
LVDS
January 2005 * REV - 3
www.azmicrotek.com
4
AZ12000
AZ12001
AZ12000 (PECL OUTPUT) DC CHARACTERISTICS
(V
CC
= +3.0 to +5.5 V, V
EE
= GND)
Symbol
V
BB
R
PD
I
CS
V
HCTL
V
LCTL
V
OH
Output LOW Voltage
1
V
OL
Q
Q
¯
Characteristic
Reference Voltage
REFIN Pull-Down resistor
to V
BB
REFOUT
Current Source
¯¯¯¯¯¯¯
High level integrator output
Low level integrator output
Output HIGH Voltage
1
Q
Q
¯
V
CC
-1085
V
CC
-1830
V
CC
-1165
V
CC
-880
V
CC
-1555
V
CC
-880
V
CC
-1025
V
CC
-1810
V
CC
-1165
V
CC
-880
V
CC
-1620
V
CC
-880
V
CC
-1025
V
CC
-1810
V
CC
-1165
V
CC
-955
V
CC
-1705
-40°C
Min
Max
V
CC
V
CC
-1.38
-1.26
0°C
Min
V
CC
-1.38
Max
V
CC
-1.26
Min
V
CC
-1.38
25°C
Typ
V
CC
-1.31
470
4.0
V
CC
-1.0
V
EE
+0.5
V
CC
-880
V
CC
-1620
V
CC
-880
V
CC
-1025
V
CC
-1810
V
CC
-1165
V
CC
-880
V
CC
-1620
V
CC
-880
85°C
Max
V
CC
-1.26
Min
V
CC
-1.38
Max
V
CC
-1.26
Unit
V
Ω
ma
V
V
mV
mV
Input HIGH Voltage,
PECL/ECL
V
IH
EXTVCO
EXTVCO
¯¯¯¯¯¯¯¯
Input LOW Voltage,
PECL/ECL
V
IL
EXTVCO
EXTVCO
¯¯¯¯¯¯¯¯
Input HIGH Voltage,
TTL/CMOS
CPPOL
V
IH
VCOSEL
DS2
DS1
Input HIGH Voltage,
TTL/CMOS
CPPOL
V
IL
VCOSEL
DS2
DS1
I
CC
(I
EE
)
Power Supply Current
1. Load is 50Ω to V
CC
-2V
mV
V
CC
-1810
V
CC
-1475
V
CC
-1810
V
CC
-1475
V
CC
-1810
V
CC
-1475
V
CC
-1810
V
CC
-1475
mV
V
EE
+2.0
V
EE
+2.0
V
EE
+2.0
V
EE
+2.0
V
V
EE
+0.8
V
EE
+0.8
V
EE
+0.8
V
EE
+0.8
V
55
58
45
58
60
mA
January 2005 * REV - 3
www.azmicrotek.com
5
